Layered crossbar for interconnection of multiple processors and shared memories

1. An apparatus comprising:

a plurality of crossbar interconnections between crossbar switches in a multi-stage crossbar network configured to process a plurality of memory transactions between a plurality of processors and a plurality of shared memory banks, wherein at least one crossbar interconnection comprises a first interface on a first crossbar switch and a second interface on a second crossbar switch; and

wherein the first interface comprises a first tag generator and the second interface comprises a second tag generator, wherein for an individual memory transaction, the first and second tag generators are configured to independently generate identical memory transaction identifiers for the memory transaction, and wherein the first crossbar switch is configured to match the memory transaction identifier of a memory transaction result received from the second crossbar switch with the memory transaction identifier of a corresponding memory transaction request that was previously sent to the second crossbar switch.

2. The apparatus of claim 1 wherein the first tag generator independently generates the memory transaction identifier for a memory transaction request before the memory transaction request is sent to the second crossbar switch, and wherein the second tag generator independently generates a memory transaction identifier for the memory transaction request after the memory transaction request is received by the second crossbar switch.

3. The apparatus of claim 1 wherein the memory transaction request comprises a command and a memory address.

4. The apparatus of claim 1 , wherein the memory transaction request comprises a command, a memory address, and data.

5. The method of claim 1 , wherein the memory transaction result comprises an acknowledgement.

6. The method of claim 1 wherein the memory transaction result comprises data.

7. The apparatus of claim 1 , wherein the multi-stage crossbar network comprises:

a plurality of first-stage crossbar switches; and

a plurality of second-stage crossbar switches;

wherein the plurality of first-stage of crossbar switches is configured to provide a communications path between the plurality of processors and the plurality of second-stage crossbar switches; and

wherein the plurality of second-stage crossbar switches is configured to provide a communications path between the plurality of first-stage crossbar switches and the plurality of shared memory banks.

8. The apparatus of claim 1 wherein the multi-stage crossbar network comprises:

a plurality of first-stage crossbar switches;

a plurality of second-stage crossbar switches; and

a plurality of third-stage crossbar switches;

wherein the plurality of first-stage of crossbar switches is configured to provide a communications path between the plurality of processors and the plurality of second-stage crossbar switches;

wherein the plurality of second-stage crossbar switches is configured to provide a communications path between the plurality of first-stage crossbar switches and the plurality of third-stage crossbar switches; and

wherein the plurality of third-stage crossbar switches is configured to provide a communications path between the plurality of second-stage crossbar switches and the plurality of shared memory banks.

9. The apparatus of claim 1 , wherein the multi-stage crossbar network comprises:

a plurality of first-stage crossbar switches;

a plurality of second-stage crossbar switches;

a plurality of third-stage crossbar switches; and

a plurality of fourth-stage crossbar switches;

wherein the plurality of first-stage of crossbar switches is configured to provide a communications path between the plurality of processors and the plurality of second-stage crossbar switches;

wherein the plurality of second-stage crossbar switches is configured to provide a communications path between the plurality of first-stage crossbar switches and the plurality of third-stage crossbar switches;

wherein the plurality of third-stage crossbar switches is configured to provide a communications path between the plurality of second-stage crossbar switches and the plurality of fourth-stage crossbar switches; and

wherein the plurality of fourth-stage crossbar switches is configured to provide a communications path between the plurality of third-stage crossbar switches and the plurality of shared memory banks.

10. The apparatus of claim 1 , wherein at least one of the first and second tag generators is a first-in-first-out buffer list comprising a set of tags, wherein each tag is used by the crossbar switch as a memory transaction identifier.

11. The apparatus of claim 1 , wherein at least one of the first and second tag generators is a counter that increments a count each time a tag is generated, wherein each generated tag is used by the crossbar switch as a memory transaction identifier.

12. The apparatus of claim 1 , wherein at least one of the first and second tag generators is a timer and each tag is a timestamp, wherein each generated tag is used by the crossbar switch as a memory transaction identifier.

13. A method comprising:

sending a memory transaction request via a communications path from one of a plurality of processors to one of a plurality of shared memory banks, wherein the communications path is provided by a multi-stage crossbar network comprising a plurality of crossbar interconnections between crossbar switches, wherein at least one crossbar interconnection comprises a first crossbar interface comprising a first tag generator and a second crossbar interface comprising a second tag generator;

storing at the first crossbar interface, a first memory transaction identifier corresponding to the memory transaction request, wherein the first memory transaction identifier is independently generated by the first tag generator; and

storing at the second crossbar interface, a second memory transaction identifier corresponding to the memory transaction request, wherein the second memory transaction identifier is independently generated by the second tag generator, and wherein the first and second memory transaction identifiers are identical.

14. The method of claim 13 , wherein the memory transaction request comprises a command and a memory address.

15. The method of claim 13 , wherein the memory transaction request comprises a command, a memory address, and data.

16. The method of claim 13 further comprising:

sending a memory transaction result and a corresponding memory transaction identifier from the second crossbar switch to the first crossbar switch via the crossbar interconnection.

17. The method of claim 16 , further comprising:

determining at the first crossbar interface that the memory transaction identifier corresponding to the memory transaction result matches a memory transaction identifier corresponding to a previously processed memory transaction request.

18. The method of claim 16 , wherein the memory transaction result comprises an acknowledgement.

19. The method of claim 16 , wherein the memory transaction result comprises data.

20. A method comprising:

receiving a memory transaction request at a crossbar switch, independently generating a local memory transaction identifier corresponding to the first memory transaction request, storing the memory transaction identifier at the crossbar switch, and sending the memory transaction request to an adjacent crossbar switch; and

receiving a memory transaction result and a corresponding memory transaction identifier from an adjacent crossbar switch, the memory transaction identifier corresponding to the received memory transaction result having been independently generated by the adjacent crossbar switch, and determining that the received memory transaction identifier corresponding to the received memory transaction result is identical to the memory transaction identifier corresponding to the previously sent memory transaction request.