Contacting scheme for large and small area semiconductor light emitting flip chip devices
View Patent ↗A light emitting device includes a layer of first conductivity type, a layer of second conductivity type, and a light emitting layer disposed between the layer of first conductivity type and the layer of second conductivity type. A via is formed in the layer of second conductivity type, down to the layer of first conductivity type. The vias may be formed by, for example, etching, ion implantation, diffusion, or selective growth of at least one layer of second conductivity type. A first contact electrically contacts the layer of first conductivity type through the via. A second contact electrically contacts the layer of second conductivity type. A ring that surrounds the light emitting layer and is electrically connected to the first contact electrically contacts the layer of first conductivity type.
1. A device comprising:
a semiconductor structure comprising a light emitting layer disposed between a layer of first conductivity type and a layer of second conductivity type;
a plurality of vias formed in the layer of second conductivity type, each of the vias extending to the layer of first conductivity type, and each of the vias being completely surrounded by the layer of second conductivity type;
at least one first contact electrically contacting the layer of first conductivity type through at least one of the plurality of vias;
a second contact electrically contacting the layer of second conductivity type;
a mount, wherein the mount comprises one of a submount and a board;
first and second interconnects, wherein the first interconnect is disposed between the first contact and the mount, the second interconnect is disposed between the second contact and the mount, and one of the first and second interconnects is an elemental metal.
2. The device of claim 1 wherein at least one of the first and second interconnects comprises gold.
3. The device of claim 1 wherein one of the first and second contacts comprises gold.
4. The device of claim 1 wherein at least one of the vias is disposed between the semiconductor structure and the second interconnect.
5. The device of claim 1 wherein the layer of first conductivity type and the layer of second conductivity type comprise gallium and nitrogen.
6. The device of claim 1 wherein the layer of first conductivity type and the layer of second conductivity type comprise aluminum and phosphorus.
7. The device of claim 1 wherein each of the vias has a width ranging from about 2 μm to about 100 μm.
8. The device of claim 1 wherein each of the vias has a width ranging from about 10 μm to about 50 μm.
9. The device of claim 1 further comprising a substrate disposed on a surface of the semiconductor structure opposite a surface on which the second contact is disposed.
10. The device of claim 1 wherein each of the vias comprises a hole in the semiconductor structure.
11. The device of claim 1 wherein each of the vias comprises a region of first conductivity type material surrounded by second conductivity type material.
12. A device comprising:
a semiconductor structure comprising a light emitting layer disposed between a layer of first conductivity type and a layer of second conductivity type;
a via formed in the layer of second conductivity type, the via extending to the layer of first conductivity type;
a first contact electrically contacting the layer of first conductivity type through the via;
a second contact electrically contacting the layer of second conductivity type; and
a ring electrically contacting the layer of first conductivity type, wherein the ring substantially surrounds the light emitting region;
a mount, wherein the mount comprises one of a submount and a board;
first and second interconnects, wherein the first interconnect electrically connects the mount to one of the first contact and the ring, the second interconnect electrically connects the second contact to the mount, and one of the first and second interconnects is an elemental metal.
13. The device of claim 12 wherein at least one of the first and second interconnects comprises gold.
14. The device of claim 12 wherein one of the first and second contacts comprises gold.
15. The device of claim 12 wherein the layer of first conductivity type and the layer of second conductivity type comprise gallium and nitrogen.
16. The device of claim 12 wherein the layer of first conductivity type and the layer of second conductivity type comprise aluminum and phosphorus.
17. The device of claim 12 further comprising a substrate disposed on a surface of the semiconductor structure opposite a surface on which the second contact is disposed.
18. The device of claim 12 wherein the via comprises a hole in the semiconductor structure.
19. The device of claim 12 wherein the via comprises a region of first conductivity type material surrounded by second conductivity type material.