IP Library Granted Patent US 7,763,501
Granted Patent B2
US 7,763,501 · App. 11/467,687 · Granted Jul 27, 2010

Forming interconnects

Assignee: Plastic Logic Limited
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Quick Facts
Patent No.
US 7,763,501
App. No.
11/467,687
Granted
Jul 27, 2010
Kind
B2
Abstract

A method for forming an electronic device, comprising: forming a first conductive or semiconductive layer; forming a sequence of at least on insulating layer and at least one semiconducting layer over the first conductive or semiconductive layer; locally depositing solvents at a localized region of the insulating layer so as to dissolve the sequence of insulating and semiconducting layers in the region to leave a void extending through the sequence of layer; and depositing conductive or semiconductive material in the void.

Claims (18)

1. An electronic device formed by:

forming a first conductive or semiconductive layer;

forming a sequence of at least one insulating layer and at least one semiconducting layer over the first conductive or semiconductive layer;

locally depositing solvents at a localized region of the sequence and forming a void in the sequence accompanied by redepositing material dissolved to form said void at a side of the void; and

depositing conductive or semiconductive material in the void.

2. An electronic device formed by:

forming a first conductive or semiconductive layer;

forming a soluble insulating or semiconducting layer over the first conductive or semiconductive layer;

locally depositing a solvent at a localized region of the soluble insulating or semiconducting layer, dissolving the soluble insulating or semiconducting layer, forming a void in said soluble insulating or semiconducting material and redepositing material dissolved to form said void at a side of the void; and

depositing conductive or semiconductive material in the void.

3. A logic circuit, display or memory device comprising a plurality of devices as claimed in claim 1 .

4. A logic circuit comprising a plurality of devices as claimed in claim 1 interconnected so as to perform a logical function.

5. A logic circuit as claimed in claim 4 , wherein at least a first one of the devices is connected to another of the devices by means of conductive material located in a void formed through at least one layer of the first one of the devices.

6. A display device comprising an optically active region switchable by an electronic device as claimed in claim 1 , the electronic device being coupled to the optically active region by means of conductive material located in a void formed through at least one layer of the device.

7. A logic circuit, display or memory device comprising a plurality of devices as claimed in claim 2 .

8. A logic circuit comprising a plurality of devices as claimed in claim 2 interconnected so as to perform a logical function.

9. A logic circuit as claimed in claim 8 , wherein at least a first one of the devices is connected to another of the devices by means of conductive material located in a void formed through at least one layer of the first one of the devices.

10. A display device comprising an optically active region switchable by an electronic device as claimed in claim 2 , the electronic device being coupled to the optically active region by means of conductive material located in a void formed through at least one layer of the device.

Assignments (3)
CHANGE OF NAME Recorded May 5, 2016
From: PLASTIC LOGIC LIMITED
To: FLEXENABLE LIMITED
Reel/Frame 038617/0662 →
RELEASE OF SECURITY INTEREST Recorded May 12, 2011
From: STATE CORPORATION "RUSSIAN CORPORATION OF NANOTECHNOLOGIES"
To: PLASTIC LOGIC LIMITED
Reel/Frame 026271/0377 →
SECURITY AGREEMENT Recorded Aug 3, 2010
From: PLASTIC LOGIC LIMITED
To: STATE CORPORATION "RUSSIAN CORPORATION OF NANOTECHNOLOGIES"
Reel/Frame 024776/0357 →
Priority Claims (2)
GB 9930217.6 · Dec 21, 1999 · national
GB 0009917.6 · Apr 20, 2000 · national
Continuity (3)
Continuation 1017617300 · Jun 21, 2002
Continuation In Part PCTGB000494000 · Dec 21, 2000
Related Publication 20060286726A1 · Dec 21, 2006