IP Library Granted Patent US 7,986,736
Granted Patent B2
US 7,986,736 · App. 11/467,914 · Granted Jul 26, 2011

Ultra wideband baseband chip with intelligent array radio and method of use thereof

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Quick Facts
Patent No.
US 7,986,736
App. No.
11/467,914
Granted
Jul 26, 2011
Kind
B2
Abstract

An ultra wideband receiver, based on multiband orthogonal frequency division multiplexing (MB-OFDM), combines digital data from multiple channels after signal processing and before decoding. The receiver provides a master controller that synthesizes packet synchronization, frame synchronization, and sampling frequency offset information from multiple channels into signals that simultaneously control all channels of the receiver.

Claims (35)

1. A receiver, comprising:

a plurality of channels for receiving a signal, wherein each channel receives the signal independently, each channel having an analog-to-digital converter for an in phase (I) signal of the received signal and an analog-to-digital converter for a quadrature (Q) signal of the received signal;

each channel further having a signal processing block coupled to the I and Q analog-to-digital converters; and

a data combiner coupled to the signal processing blocks of each channel, that combines the I signals from each channel and combines the Q signals from each channel

wherein the signal processing blocks are further coupled to a controller, the controller comprising a combiner that combines incoming correlation values from the plurality of channels

wherein the controller further includes a master symbol sync, a master frame sync coupled to the master symbol sync, and a master sampling frequency offset feedback control coupled to the master frame sync;

wherein the master symbol sync process incoming symbol synchronization correlations values from the plurality of channels to produce symbol boundary and packet detection control information;

wherein the master frame sync determines a start of channel estimation symbols, header symbols and data symbols with a received packet;

wherein the master sampling frequency offset feedback control provides control information to a symbol sync of the signal processing block and a phase locked loop that drives a clock using sampling frequency offset estimates from each channel.

2. The receiver of claim 1 , wherein the values from the plurality of channels are selectable.

3. The receiver of claim 2 , wherein the selection is based on signal-to-noise ratio of the channels.

4. The receiver of claim 1 , wherein data combiner combines the signals using a weighted average based on the SNR of the signals.

5. The receiver of claim 1 , wherein the data combiner combines the signals using a simple average.

6. The receiver of claim 1 , wherein the data combiner combines values from enabled channels of the plurality of channels.

7. The receiver of claim 1 , wherein the plurality of channels includes three channels.

8. The receiver of claim 1 , further comprising a decoder coupled to the data combiner that reverses encoding functions of a transmitter.

9. The receiver of claim 1 , wherein the signal processing block shares a fast Fourier transform with a transmitter.

10. The receiver of claim 4 , wherein the data combiner is located after the signal processing blocks.

11. The receiver of claim 1 , wherein each signal processing block includes a channel equalizer.

12. A method, comprising:

receiving a signal;

for a plurality of channels, each of which receives the signal independently,

converting from analog to digital an in-phase (I) signal of the received

signal and a quadrature (Q) signal of the received signal;

signal processing each converted signal; and

after the processing, combining the I signals from each channel and combining the Q signals from each channel;

combining, by a combiner in a controller, incoming correlation values from the plurality of channels;

processing, by the controller, incoming symbol synchronization correlations values from the plurality of channels to produce symbol boundary and packet detection control information;

determining, by the controller, a start of channel estimation symbols, header symbols and data symbols with a received packet; and

providing, by the controller, control information for the signal processing and to a phase locked loop that drives a clock using sampling frequency offset estimates from each channel.

13. The method of claim 12 , wherein the values from the plurality of channels are selectable.

14. The method of claim 13 , wherein the selection is based on signal-to-noise ratio of the channels.

15. The method of claim 12 , wherein the combiner combines the signals using a simple average.

16. The method of claim 12 , wherein the plurality of channels includes three channels.

17. The method of claim 12 , further comprising reversing encoding functions of a transmitter.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2022
From: V-SILICON SEMICONDUCTOR (HEFEI) CO. LTD.
To: V-SILICON SEMICONDUCTOR (HANGZHOU) CO. LTD.
Reel/Frame 061399/0930 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2018
From: V-SILICON INC.; V-SILICON INTERNATIONAL INC.
To: V-SILICON SEMICONDUCTOR (HEFEI) CO. LTD.
Reel/Frame 047220/0398 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2018
From: SIGMA DESIGNS, INC.
To: V-SILICON INC.; V-SILICON INTERNATIONAL INC.
Reel/Frame 046330/0733 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2006
From: NGUYEN, HUNG C.; FRENCH, CATHERINE A.; DESAI, JAYESH; LU, RUOYANG; PIROOZ, ALI D.
To: SIGMA DESIGNS, INC.
Reel/Frame 018182/0288 →