Systems for display images including two gate drivers disposed on opposite sides of a pixel array
View Patent ↗Systems for displaying images are provided, comprising a pixel array, a first gate driver and a second gate driver. The first gate driver is disposed on a first side of the pixel array and the second gate driver is disposed on a second side opposite to the first side. The first gate driver comprises a first shift register and a first AND gate. The first shift register receives a first clock signal and a start signal to generate a first control signal. The first AND gate receives a second clock signal and the first control signal to generate a first gate signal. The second gate driver comprises a second shift register and a second AND gate. The second shift register receives a second clock signal and a start signal to generate a second control signal. The second AND gate receives a first clock signal and the second control signal to generate a second gate signal.
1. A system for displaying images, comprising:
a pixel array;
a first gate driver disposed on a first side of the pixel array, comprising:
a first shift register receiving a first clock signal and a start signal to generate a first control signal; and
a first AND gate receiving a second clock signal and the first control signal to generate a first gate signal; and
a second gate driver disposed on a second side opposing to the first side, comprising:
a second shift register receiving the first gate signal and the second clock signal to generate a second control signal; and
a second AND gate receiving the first clock signal and the second control signal to generate a second gate signal.
2. The system as claimed in claim 1 , wherein a duty cycle of the first clock signal is less than 50%.
3. The system as claimed in claim 1 , wherein a duty cycle of the second clock signal is less than 50%.
4. The system as claimed in claim 1 , wherein the first clock signal is a non-overlap clock signal with the second clock signal.
5. The system as claimed in claim 1 , wherein the first clock signal and the second clock signal are generated by a non-overlap clock signal generator.
6. The system as claimed in claim 1 , wherein the first shift register comprises:
a first clock inverter having an input terminal receiving the start signal and an output terminal, activated when the first clock signal is high;
a first inverter having an input terminal coupled to the output terminal of the first clock inverter, and an output terminal for outputting the first control signal; and
a second clock inverter having an input terminal coupled to the output terminal of the first inverter, and an output terminal coupled to the output terminal of the first clock inverter.
7. The system as claimed in claim 1 , wherein the first gate driver having a plurality of first driving units and the second gate driver having a plurality of second driving units.
8. The system as claimed in claim 1 , further comprising a display panel, wherein the pixel array, the first driving unit and the second driving unit forms a portion of the display panel.
9. The system as claimed in claim 8 , further comprising an electronic device, wherein the electronic device comprises:
the display panel; and
an input device coupled to the display panel and operative to provide input to the display panel such that the display panel displays images.
10. The system as claimed in claim 9 , wherein the electronic device is a mobile phone, digital camera, PDA (personal digital assistant), notebook computer, desktop computer, television, car display, or portable DVD player.