High frequency divider state correction circuit
View Patent ↗The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
1. A self-correcting state circuit, comprising:
a first flip flop configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input;
a second flip flop coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the second data input;
a first correction circuit coupled to the second flip flop and configured to generate a corrected output; and
a third flip flop coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input wherein the first correction circuit is further configured to generate the corrected output based on the inverse of the first output, the inverse of the second output, and the inverse of the third output.
2. The circuit of claim 1 , wherein each of the first flip flop, the second flip flop, and the third flip flop is a D-type flip flop.
3. The circuit of claim 1 , further comprising a fourth flip flop coupled to the third flip flop and configured to receive the clock input and to receive the third output as a fourth data input, and to generate a fourth output in response to the clock input and the third output.
4. The circuit of claim 1 , further comprising a first select signal.
5. The circuit of claim 4 , wherein the first select signal is the inverse of the first output.
6. The circuit of claim 4 , wherein the first select signal is further configured as the first data input.
7. The circuit of claim 1 , wherein the first correction circuit comprises a plurality of CMOS devices.
8. The circuit of claim 7 , wherein the first correction circuit comprises:
a first PMOS coupled to a supply voltage and configured to operate in response to the inverse of the second output;
a second PMOS coupled to the first PMOS and configured to operate in response to the inverse of the first output;
a third PMOS coupled to the first PMOS and configured to operate in response to the inverse of the third output;
a first NMOS coupled to the second PMOS and to ground and configured to operate in response to the inverse of the second output;
a second NMOS coupled to the third PMOS and configured to operate in response to the inverse of the first output; and
a third NMOS coupled to the second NMOS and to ground and configured to operate in response to the inverse of the third output.
9. The circuit of claim 1 , wherein each of the first output, the second output, and the third output is represented as a single bit.
10. The circuit of claim 1 , wherein the first correction circuit is further configured to advance from a current state output to a future state output in accordance with a pre-determined rule.
11. The circuit of claim 10 , wherein the pre-determined rule is a bitwise right circular shift operation and wherein a rightmost bit is inverted as it is transferred into a leftmost position as a result of the right circular shift operation.