REDUCED COMPONENT DISPLAY DRIVER AND METHOD
A display driver circuit for driving display elements in a row of a display array, includes an m input, n-bit input multiplexer; a digital to analog converter, and a one input, m output, analog output multiplexer. A clock source, clocks the input and output multiplexers, to sequentially provide an analog output corresponding to one of said m n-bit inputs, at a corresponding one of said m outputs of said output multiplexer.
1 . A display driver circuit for driving display elements in a row of a display array, said display driver circuit comprising:
m inputs;
an input selector, having m n-bit inputs and an n-bit output for providing a selected one of said m n-bit inputs, said m n-bit inputs interconnected with said m inputs;
an n-bit digital to analog converter, receiving said n-bit output of said selector, and providing an analog output;
an output selector having an analog input interconnected with said analog output of said digital to analog converter, and m analog outputs providing said analog input at a selected one of said m analog outputs;
a clock source, to clock said input and output selectors, to sequentially provide an analog output corresponding to one of said m n-bit inputs, at a corresponding one of said m analog outputs of said output selector.
2 . The circuit of claim 1 , wherein said digital to analog converter comprises an n-bit decoder.
3 . The circuit of claim 2 , wherein said digital to analog converter comprises a buffer.
4 . The circuit of claim 3 , wherein said buffer comprises an operational amplifier.
5 . The circuit of claim 2 , further comprising a row selector to enable a row of display elements within said array of display elements.
6 . The circuit of claim 1 , further comprising
a further m inputs;
a second input selector, having m n-bit inputs and an n-bit output for providing a selected one of said m n-bit inputs, said m n-bit inputs interconnected with said further m inputs;
a second n-bit digital to analog converter, receiving said n-bit output of said second input selector, and providing a second analog output;
a second output selector having an analog input interconnected with said second analog output of said second digital to analog converter, and m analog outputs providing a signal at its input at a selected one of its m outputs;
wherein said clock source clocks said second input and second output selectors, to sequentially provide an analog output corresponding to one of said further m n-bit inputs, at a corresponding one of said m analog outputs of said second output selector.
7 . The circuit of claim 6 , further comprising a buffer interconnected to each of said m outputs.
8 . The circuit of claim 6 , further comprising a storage capacitor interconnected to each of said m analog outputs of said output selector.
9 . The circuit of claim 8 , further comprising a switch interconnected to each of said storage capacitors, to control when voltages stored in said storage capacitors are provided to said display array.
10 . A method of driving an analog display array, said method comprising
receiving m digital values, representing m pixels to be displayed on said display array;
multiplexing said m digital values;
sequentially converting said m digital values to corresponding analog signals, using a single digital to analog converter, to provide m sequential analog values;
demultiplexing said m sequential analog values to create m analog signals to drive m elements in a row of said analog display array.
11 . The method of claim 10 , further comprising sequentially providing said m analog signals to said analog display array.
12 . The method of claim 10 , further comprising concurrently providing said m analog signals to said analog display array.
13 . The method of claim 11 , further comprising buffering each of said m analog signals.
14 . The method of claim 10 , further comprising providing a clock signal to synchronously perform said multiplexing and demultiplexing.
15 . The method of claim 14 , further comprising repeating said receiving, multiplexing, and converting, demultiplexing at a rate at which rows of said array are to be updated.
16 . The method of claim 15 , wherein said clock signal is generated at a rate that is at least m times as great as said rate at which rows of said array are to be updated.
17 . The method of claim 12 , further comprising charging capacitors with said m analog signals, prior to said concurrently providing.
18 . An electronic device comprising:
a display array, having display elements arranged in rows and columns;
said display driver circuit interconnected with said display array, said display driver circuit comprising:
m inputs;
an input selector, having m n-bit inputs and an n-bit output for providing a selected one of said m n-bit inputs, said m n-bit inputs interconnected with said m inputs;
an n-bit digital to analog converter, receiving said n-bit output of said selector, and providing an analog output for driving said display elements;
an output selector having an analog input interconnected with said analog output of said digital to analog converter, and m analog outputs providing said analog input at a selected one of said m outputs;
a clock source, to clock said input and output selectors, to sequentially provide an analog output corresponding to one of said m n-bit inputs, at a corresponding one of said m analog outputs of said output selector.
19 . The device of claim 18 , wherein said display array comprises a two dimensional array of field effect transistors (FETs), with sources of said FETs in each column of said array interconnected to a source line, and gates of said FETs in each row of said array connected to a gate line, wherein each of said m analog outputs of said output selector is in communication with one of said source lines of said display array.
20 . The device of claim 19 , further comprising a gate driver sequentially driving said gate lines at a row refresh rate.
21 . The device of claim 20 , wherein said clock source is clocked at a rate at least m times as great as said row refresh rate.
22 . The device of claim 21 , wherein each of said display elements has sufficient capacitance to maintain a state of said display element until all rows of said array have been refreshed at said row refresh rate.
23 . The device of claim 18 , wherein each of said display elements comprises one of an LCD, OLED, or an SED display element.
24 . A display driver circuit for driving display elements in a row of a display array, said display driver circuit comprising:
an m input, n-bit input multiplexer;
a digital to analog converter, receiving an n-bit output from said n-bit multiplexer;
a one input, m output, analog output multiplexer;
a clock source, to clock said input and output multiplexers, to sequentially provide an analog output corresponding to one of said m n-bit inputs, at a corresponding one of said m outputs of said output multiplexer.
25 . The circuit of claim 24 , wherein said digital to analog converter comprises an n-bit decoder.
26 . The circuit of claim 25 , wherein said digital to analog converter comprises a buffer.
27 . The circuit of claim 25 , further comprising a row selector to enable a row of display elements within said array of display elements.
28 . The circuit of claim 25 , further comprising a buffer interconnected to each of said m outputs.
29 . The circuit of claim 28 , further comprising a storage capacitor interconnected to each of said m analog outputs of said output selector.
30 . The circuit of claim 29 , further comprising a switch interconnected to each of said storage capacitors, to control when voltages stored in said storage capacitors are provided to said display array.