Method and apparatus for generating a reference signal and generating a scaled output signal based on an input signal

1. An integrated circuit comprising:

a first logic one reference signal generator;

a second logic one reference signal generator;

a voltage range router selectively operative to route an input signal to one of: the first logic one reference signal generator and the second logic one reference signal generator based at least on a voltage level of the input signal;

wherein the first logic one reference signal generator is selectively operative to generate a first logic one reference signal when the voltage level of the input signal is less than a threshold value;

wherein the second logic one reference signal generator is alternatively operative to generate a second logic one reference signal when the voltage level of the input signal is greater than or equal to the threshold value; and

wherein each of the first logic one reference signal generator, the second logic one reference signal generator and the voltage range router comprises one or more integrated circuit components each having at least two terminals and wherein a maximum voltage difference between any two terminals of each integrated circuit component does not exceed a voltage level of the first logic one reference signal plus a predetermined tolerance.

2. The integrated circuit of claim 1 , wherein:

each of the voltage range router, the first logic one reference signal generator and the second logic one reference signal generator comprises a plurality of single gate oxide MOSFETs; and

each single gate oxide MOSFET is connected so that a maximum voltage difference between any two terminals does not exceed a voltage level of the first logic one reference signal plus a predetermined tolerance.

3. The integrated circuit of claim 1 , wherein the first logic one voltage generator comprises:

a feedback latch;

a low range scaler operatively coupled to the feedback latch and operative to generate a preliminary first logic one reference signal when the voltage level of the input signal is less than a first preliminary voltage level, wherein the first preliminary voltage level is less than the threshold value; and

wherein the feedback latch is operative to generate the first logic one reference signal based on the preliminary first logic one reference signal when the voltage level of the input signal is less than the threshold value.

4. The integrated circuit of claim 3 , wherein the second logic one voltage generator comprises:

the feedback latch;

a high range scaler operatively coupled to the feedback latch and operative to generate a preliminary second logic one reference signal when the voltage level of the input signal is equal to the threshold value and when the voltage level of the input signal is greater than or equal to a second preliminary voltage level, wherein the second preliminary voltage level is greater than the threshold value; and

wherein the feedback latch is operative to generate the second logic one reference signal based on the preliminary second logic one reference signal when the voltage level of the input signal is greater than or equal to the threshold value.

5. The integrated circuit of claim 1 , further comprising an output buffer operative to:

buffer one of: the first logic one reference signal and the second logic one reference signal; and

generate a corresponding one of: a buffered first logic one reference signal and a buffered second logic one reference signal.

6. The integrated circuit of claim 1 , wherein the integrated circuit is integrated on a chip set circuit.

7. The integrated circuit of claim 1 , wherein the input signal is provided by a peripheral input signal source.

8. The integrated circuit of claim 1 , wherein each integrated circuit component is connected so that there is effectively no static leakage current across any integrated circuit terminal.

9. A method for generating a logic one reference signal comprising:

selectively generating a first logic one reference signal when a voltage level of an input signal is less than a threshold value;

alternatively generating a second logic one reference signal when the voltage level of an input signal is greater than or equal to the threshold value; and

wherein selectively generating a first logic one reference signal and wherein alternately generating a second logic one reference signal is performed by a plurality of integrated circuit components each having at least two terminals and wherein a maximum voltage difference between any two terminals of each integrated circuit component does not exceed a voltage level of the first logic one reference signal plus a predetermined tolerance.

10. The method of claim 9 , wherein each integrated circuit component is a single gate oxide MOSFET each connected so that a maximum voltage difference between any two terminals does not exceed the voltage level of the first logic one reference signal plus a predetermined tolerance.

11. The method of claim 9 , wherein selectively generating a first logic one reference signal when the voltage level of the input signal is less than the threshold value comprises:

generating a preliminary first logic one reference signal when the voltage level of the input signal is less than a first preliminary voltage level, wherein the first preliminary voltage level is less than the threshold value; and

generating the first logic one reference signal based on the preliminary first logic one reference signal when the voltage level of the input signal is less than the threshold value.

12. The method of claim 11 , wherein alternatively generating the second logic one reference signal when the voltage level of the input signal is greater than or equal to the threshold value comprises:

generating a preliminary second logic one reference signal when the voltage level of the input signal is equal to the threshold value and when the voltage level of the input signal is greater than or equal to a second preliminary voltage level, wherein the second preliminary voltage level is greater than the threshold value; and

generating the second logic one reference signal based on the preliminary second logic one reference signal when the voltage level of the input signal is greater than or equal to the threshold value.

13. The method of claim 9 , further comprising:

buffer one of: the first logic one reference signal and the second logic one reference signal;

generating a corresponding one of: a buffered first logic one reference signal and a buffered second logic one reference signal.

14. The method of claim 9 , wherein the input signal is provided by a peripheral input signal source.

15. The method of claim 9 , wherein each integrated circuit component is connected so that there is effectively no static leakage current across any integrated circuit terminal.

16. An integrated circuit comprising:

a voltage range router comprising a voltage range router NMOS transistor (“M N0 ”) and a voltage range router PMOS transistor (“M P0 ”), wherein a first terminal of M N0 is operatively coupled to a first terminal of M P0 thereby forming a first input of the voltage range router and wherein the first input of the voltage range router is operative to receive an input signal, and wherein a gate of M N0 is operatively coupled to a gate of M P0 thereby forming a second input of the voltage range router;

a low range scaler comprising a first low range PMOS transistor (“M P1 ”), wherein a gate of M P1 is operatively coupled to a second terminal of M N0 thereby forming a first output of the voltage range router, and wherein a source of M P1 is operatively coupled to a first voltage supply;

a high range scaler comprising a first high range NMOS transistor (“M N1 ”) and a second high range NMOS transistor (“M N2 ”), wherein a gate of M N1 is operatively coupled to a second terminal of M P0 and a first terminal of M N2 thereby forming a second output of the voltage range router, wherein a source of M N1 is operatively coupled to a gate of M N2 and a second voltage supply, and a drain of M N1 is operatively coupled to a second terminal of M N2 and a drain of M P1 ;

wherein the feedback latch comprises a first inverter, a second inverter and a third inverter, wherein an input of the first inverter is operatively coupled to: an output of the third inverter, the second terminal of M N2 , and the drains of M N1 and M P1 thereby forming a feedback latch input, wherein an output of the first inverter is operatively coupled to an input of the second inverter and an input of the third inverter, wherein the output of the second inverter is operatively coupled to the second input of the voltage range splitter, and wherein each of the first inverter, the second inverter and the third inverter are coupled to the first voltage supply and the second voltage supply;

wherein the output of the second inverter is one of: a first logic one reference signal and a second logic one reference signal; and

wherein each of M P0 , M P1 , M P2 , M N0 , M N1 and M N2 is a single gate oxide MOSFET each connected so that a maximum voltage difference between any two terminals does not exceed a voltage level of the first logic one reference signal plus a predetermined tolerance.

17. The integrated circuit of claim 16 , wherein:

a voltage level of the first logic one reference signal corresponds to a voltage level of the first voltage supply; and

a voltage level of the second logic one reference signal corresponds to the voltage level of the second voltage supply.

18. The integrated circuit of claim 16 , wherein:

the low range scaler further includes a second low range PMOS transistor (“M P2 ”), wherein a gate of M P2 is operatively coupled to the first voltage supply, wherein a first terminal of M P2 is operatively coupled to the first voltage range router output, and wherein a second terminal of M P2 is operatively coupled to the feedback latch input; and

wherein, based on a voltage level at the feedback latch input, M P2 is selectively operative to reduce current leakage across M N0 when M N0 is off.

19. The integrate circuit of claim 18 , wherein M P2 is a single gate oxide MOSFET connected so that a maximum voltage difference between any two terminals does not exceed a voltage level of the first logic one reference signal plus a predetermined tolerance.

20. The integrated circuit of claim 16 , wherein M N2 is selectively operative to reduce current leakage across M P1 when M P1 is off.

21. The integrated circuit of claim 16 , further comprising an output buffer coupled to the second input of the voltage range router wherein the output buffer is operative to:

buffer one of: the first logic one reference signal and the second logic one reference signal; and

generate a corresponding one of: a buffered first logic one reference signal and a buffered second logic one reference signal.

22. The integrated circuit of claim 16 , wherein the integrated circuit is integrated on a chip set circuit.

23. The integrated circuit of claim 16 , wherein the continuous voltage signal is provided by a peripheral input signal source.

24. An integrated circuit comprising:

a first logic one reference signal generator operatively coupled to a first voltage supply;

a second logic one reference signal generator operatively coupled to a second voltage supply, wherein a voltage level of the second voltage supply is greater than a voltage level of the first voltage supply;

a voltage range router selectively operative to route an input signal to one of: the first logic one reference signal generator and the second logic one reference generator based on at least a voltage level of the input signal, wherein the input signal has a logic one voltage level greater than the voltage level of the second voltage supply;

wherein the first logic one reference signal generator is selectively operative to generate a first logic one reference signal having a voltage level corresponding to the first voltage supply voltage level when the voltage level of the input signal is less than a threshold value;

wherein the second logic one reference signal generator is alternatively operative to generate a second logic one reference signal having a voltage level corresponding to the second voltage supply voltage level when the voltage level of the input signal is greater than or equal to the threshold value; and

each of the voltage range router, the first logic one reference signal generator and the second logic one reference signal generator comprises a plurality of single gate oxide MOSFETs, wherein each MOSFET is connected so that a maximum voltage difference between any two terminals does not exceed a voltage level of the first logic one reference signal plus a predetermined tolerance.

25. The integrated circuit of claim 24 , wherein the first logic one voltage generator comprises:

a feedback latch;

a low range scaler operatively coupled to the feedback latch and operative to generate a preliminary first logic one reference signal when the voltage level of the input signal is less than a first preliminary voltage level, wherein the first preliminary voltage level is less than the threshold value; and

wherein the feedback latch is operative to generate the first logic one reference signal based on the preliminary first logic one reference signal when the voltage level of the input signal is less than the threshold value.

26. The integrated circuit of claim 25 , wherein the second logic one voltage generator comprises:

the feedback latch;

a high range scaler operatively coupled to the feedback latch and operative to generate a preliminary second logic one reference signal when the voltage level of the input signal is equal to the threshold value and when the voltage level of the input signal is greater than or equal to a second preliminary voltage level, wherein the second preliminary voltage level is greater than the threshold value; and

wherein the feedback latch is operative to generate the second logic one reference signal based on the preliminary second logic one reference signal when the voltage level of the input signal is greater than or equal to the threshold value.

27. The integrated circuit of claim 24 , wherein the integrated circuit is integrated on a chip set circuit.

28. The integrated circuit of claim 24 , wherein each MOSFET is connected such that there is effectively no static leakage current across any terminal of the MOSFET.

29. An integrated circuit comprising:

a voltage discriminator circuit operatively coupled to a first voltage supply and a second voltage supply, wherein the second voltage supply has a voltage level greater than a voltage level of the first voltage supply, and wherein the voltage discriminator circuit is selectively operative to generate a first logic one reference signal when a voltage of an input signal is less than a threshold value, and alternatively operative to generate a second logic one reference signal when a voltage of the input signal is greater than or equal to the threshold value, wherein the input signal has a logic one value greater than the voltage level of the second voltage supply;

a first voltage scaling circuit operative to generate a preliminary scaled output signal based on the input signal and one of: the first logic one reference signal and the second logic one reference signal;

a second voltage scaling circuit operative to generate the scaled output signal based on the preliminary scaled output signal, wherein the scaled output has a logic one value corresponding to the voltage level of the first voltage supply; and

wherein each of the voltage discriminator circuit, the first voltage scaling circuit and the second voltage scaling circuit comprises one or more integrated circuit components each having at least two terminals and wherein a maximum voltage difference between any two terminals of each integrated circuit component does not exceed a voltage level of the first logic one reference signal plus a predetermined tolerance.

30. The integrated circuit of claim 29 , wherein the preliminary scaled output signal does not exceed:

the voltage level of the first voltage supply when the voltage discriminator circuit generates a first logic one reference signal; and

the voltage level of the second voltage supply when the voltage discriminator circuit generates a second logic one reference signal.

31. The integrated circuit of claim 29 , wherein:

the first logic one reference signal has a voltage level corresponding to the first voltage supply; and

the second logic one reference signal has a voltage level corresponding to the second voltage supply.

32. The integrated circuit of claim 29 , wherein the voltage discriminator circuit comprises:

a first logic one reference signal generator;

a second logic one reference signal generator;

a voltage range router selectively operative to route the input signal to one of: the first logic one reference signal generator and the second logic one reference signal generator based at least on the voltage level of the input signal;

wherein the first logic one reference signal generator is selectively operative to generate the first logic one reference signal when the voltage level of the input signal is less than the threshold value; and

wherein the second logic one reference signal generator is selectively operative to generate the second logic one reference signal when the voltage level of the input signal is greater than or equal to the threshold value.

33. The integrated circuit of claim 31 , wherein:

the first logic one voltage generator comprises:

a feedback latch;

a low range scaler operatively coupled to the feedback latch and operative to generate a preliminary first logic one reference signal when the voltage level of the input signal is less than a first preliminary voltage level, wherein the first preliminary voltage level is less than the threshold value; and

wherein the feedback latch is operative to generate the first logic one reference signal based on the preliminary first logic one reference signal when the voltage level of the input signal is less than the threshold value;

and

the second logic one voltage generator comprises:

the feedback latch;

a high range scaler operatively coupled to the feedback latch and operative to generate a preliminary second logic one reference signal when the voltage level of the input signal is equal to the threshold value and when the voltage level of the input signal is greater than or equal to a second preliminary voltage level, wherein the second preliminary voltage level is greater than the threshold value; and

wherein the feedback latch is operative to generate the second logic one reference signal based on the preliminary second logic one reference signal when the voltage level of the input signal is greater than or equal to the threshold value.

34. The integrated circuit of claim 29 , wherein the first voltage scaling circuit comprises an NMOS transistor (“M N3 ”), wherein a first terminal of M N3 is coupled to receive the input signal, wherein a gate of M N3 is coupled to receive one of: the first logic one reference signal and the second logic one reference signal; and wherein a second terminal of M N3 is coupled to the second voltage scaling circuit.

35. The integrated circuit of claim 29 , wherein the second voltage scaling circuit comprises:

a first NMOS transistor (“M N4 ”) and a second NMOS transistor (“M N5 ”);

wherein a gate of M N4 is operably coupled to a first terminal of M N5 and to the first voltage scaling circuit;

wherein a source of M N4 is operatively coupled to a gate of M N5 and to the first voltage supply; and

wherein a drain of M N4 is operatively coupled to a second terminal of M N5 .

36. The integrated circuit of claim 29 , wherein each integrated circuit component is connected so that there is effectively no static leakage current across any integrated circuit terminal.

37. A method for generating a scaled output signal comprising:

selectively generating a first logic one reference signal when a voltage level of an input signal is less than a threshold value, and alternatively generating a second logic one reference signal when the voltage level of the input signal is greater than or equal to the threshold value, wherein a voltage level of the first logic one reference signal is less than a voltage level of the second logic one reference signal, and wherein the voltage level of the second logic one reference signal is less than a logic one voltage level of the input signal;

generating a preliminary scaled output signal based on the input signal and one of the first logic one reference signal and the second logic one reference signal;

generating the scaled output signal based on the preliminary scaled output signal, wherein the scaled output has a logic one value corresponding to the voltage level of the first voltage supply; and

wherein generating one or more of a first logic one reference signal, a second logic one reference signal, a preliminary scaled output signal and a scaled output signal is performed by a plurality of integrated circuit components each having at least two terminals and wherein a maximum voltage difference between any two terminals of each integrated circuit component does not exceed a voltage level of the first logic one reference signal plus a predetermined tolerance.

38. The method of claim 37 , wherein the preliminary scaled output signal does not exceed:

the voltage level of the first voltage supply when the voltage discriminator circuit generates a first logic one reference signal; and

the voltage level of the second voltage supply when the voltage discriminator circuit generates a second logic one reference signal.

39. The method of claim 37 , wherein:

selectively generating a first logic one reference signal when the voltage level of the input signal is less than the threshold value comprises:

generating a preliminary first logic one reference signal when the voltage level of the input signal is less than a preliminary voltage level, wherein the first preliminary voltage level is less than the threshold value; and

generating the first logic one reference signal based on the preliminary first logic one reference signal when the voltage level of the input signal is less than the threshold value;

and

alternatively generating a second logic one reference signal when the voltage of the input signal is greater than or equal to the threshold value comprises:

generating a preliminary second logic one reference signal when the voltage level of the input signal is equal to the threshold value and when the voltage level of the input signal is greater than or equal to a second preliminary voltage level, wherein the second preliminary voltage level is greater than the threshold value; and

generating the second logic one reference signal based on the preliminary second logic one reference signal when the voltage level of the input signal is greater than or equal to the threshold value.

40. The method of claim 37 , wherein each integrated circuit component is connected so that there is effectively no static leakage current across any integrated circuit terminal.