Reduced component digital to analog decoder and method
View Patent ↗An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.
1. A method of converting an n-bit digital input signal into an analog output signal, comprising:
selecting a first analog voltage from analog voltages above a first threshold using a plurality of only p-type transistor switches, in dependence on said n-bit digital input signal;
selecting a second analog voltage from analog voltages below a second threshold that is above said first threshold, using a plurality of only n-type transistor switches, in dependence on said n-bit digital input signal;
selecting as said analog output, one of said first analog voltage and said second analog voltage, in dependence on said n-bit digital input signal.
2. The method of claim 1 , wherein each of said p-type transistor switches is formed as a PMOS transistor switch, and each of said n-type transistor switches is formed as an NMOS transistor switch.
3. The method of claim 2 , wherein each of said p-type transistor switches is formed using a single PMOS transistor, and each of said n-type transistor switches is formed using a single NMOS transistor.
4. The method of claim 1 , wherein said first analog voltage and said second analog voltage are each selected using n−1 of said n-bit digital input signal.
5. The method of claim 4 , wherein one of said first analog voltage and said second analog voltage is selected using one bit of said n-bit digital input signal.
6. The method of claim 1 , further comprising:
periodically varying said analog voltages above said first threshold;
and said analog voltages below said second threshold, in dependence on a clock signal.
7. The method of claim 1 , wherein said analog voltages above said first threshold and said analog voltages below said second threshold are provided using a voltage divider, and wherein voltages applied to said voltage divider are varied in dependence on said clock signal.
8. The method of claim 1 , wherein said analog output signal drives an element of a display.
9. A method of converting a digital value into an analog output signal, comprising:
receiving said digital value as n bits;
decoding n−1 of said bits using an n−1 bit PMOS decoder formed without NMOS transistors, to provide an analog PMOS decoder output signal having a value above a threshold voltage;
decoding n−1 of said bits using an n−1 bit NMOS decoder formed without PMOS transistors, to provide an NMOS decoder output signal, having a value below said threshold;
selecting one of said NMOS decoder output, and said PMOS decoder output signals to provide said analog output signal.
10. A digital to analog decoder comprising:
n inputs for receiving an n bit digital input;
an n−1 bit PMOS decoder formed without NMOS transistors, to decode n−1 of said digital input to provide an analog PMOS decoder output signal having a value above a threshold voltage;
an n−1 bit NMOS decoder formed without PMOS transistors, to decode n−1 of said digital input to provide an analog NMOS decoder output signal having a value below said threshold voltage;
a selector for selecting one of said NMOS decoder output, and said PMOS decoder output signals to provide said analog output signal.
11. The digital to analog decoder of claim 10 , wherein said n−1 bit PMOS decoder comprises 2 n −2 PMOS transistor switches, and wherein said n−1 bit NMOS decoder, comprises 2 n −2 NMOS transistor switches.
12. The digital to analog decoder of claim 11 , wherein said selector is formed as a PMOS transistor and an NMOS transistor switch.
13. The digital to analog decoder of claim 10 , wherein said n−1 bit NMOS decoder comprises a control input to substantially power-down said n−1 bit NMOS decoder, and wherein said n−1 bit PMOS decoder comprises a control input to substantially power-down said n−1 bit PMOS decoder.
14. The digital to analog decoder of claim 13 , wherein said control inputs are controlled by one of said n inputs, to substantially power-down the one of said NMOS decoder and said PMOS decoder not providing said analog output signal.
15. A digital to analog decoder comprising p-type transistor and n-type transistor switches:
n inputs for receiving an n bit digital input;
a plurality of only p-type transistor switches for selecting a first analog voltage from analog voltages above a first threshold in dependence on said n-bit digital input signal;
a plurality of only n-type transistor switches for selecting a second analog voltage from analog voltages below a second threshold that is above said first threshold, in dependence on said n-bit digital input signal;
a selector for selecting one of said first and second analog voltages to provide said analog output signal.
16. The digital to analog decoder of claim 15 , further comprising 2 n analog inputs for receiving said analog voltages above said threshold, and below said threshold.
17. The digital to analog decoder of claim 16 , wherein 2 n−1 of said analog inputs are for receiving said analog voltages above said threshold, and 2 n−1 of said analog inputs are for receiving said analog voltages below said threshold.
18. The digital to analog decoder of claim 15 , wherein each of said p-type transistor switches is formed as a PMOS transistor switch, and each of said n-type transistor switches is formed as NMOS transistor switch.
19. The digital to analog decoder of claim 18 , wherein each of said p-type transistor switches is formed using a single PMOS transistor, and each of said n-type transistor switches is formed using a single NMOS transistor.
20. The digital to analog decoder of claim 19 , wherein said selector is formed as a PMOS transistor and an NMOS transistor switch.
21. The digital to analog decoder of claim 15 , wherein said p-type transistors are interconnected to form an n−1 bit p-type decoder, and further comprising a control input interconnected to at least some of those of said plurality of p-type transistor switches, to prevent analog signals provided to said n−1 bit p-type decoder from propagating through said p-type transistor switches, to an output of said n−1 bit p-type decoder.
22. The digital to analog decoder of claim 21 , wherein said p-type transistors are arranged in columns, and wherein said control input turns off those of said p-type transistors in a column receiving 2 n− of said analog inputs.
23. The digital to analog decoder of claim 15 , wherein said n-type transistors are interconnected to form an n−1 bit n-type decoder, and further comprising a control input interconnected to at least some of those of said plurality of n-type transistor switches, to prevent analog signals provided to said n−1 bit n-type decoder from propagating through said n-type transistor switches, to an output of said n−1 bit n-type decoder.
24. The digital to analog decoder of claim 23 , wherein said n-type transistors are arranged in columns, and wherein said control input turns off those of said n-type transistors in a column receiving 2 n− of said analog inputs.
25. A digital to analog decoder circuit comprising:
the digital to analog decoder of claim 15 ;
at least one multiplexer to vary analog voltages applied to said analog inputs in alternate cycles of an applied clock.
26. The digital to analog decoder circuit of claim 25 , further comprising:
a resistor network for providing said analog voltages applied to said analog inputs.
27. The digital to analog decoder circuit of claim 26 , further comprising:
a data condition to alter digital data presented to said digital inputs in alternate clock cycles of said applied clock.
28. The digital to analog decoder circuit of claim 27 , wherein:
said data conditioner comprises an inverter for inverting said n bits in alternate clock cycles of said applied clock.