Temperature control in an integrated circuit
View Patent ↗One example of a test board includes first and second communication ports configured for communication with a master device and a DUT, respectively. A bit error rate tester of the test board is arranged for communication with the master device and with the DUT by way of the first and second communication ports, respectively, and the bit error rate tester includes at least one IC whose maximum data rate is temperature sensitive. Finally, the test board includes a temperature control system arranged to control the IC temperature so that a maximum data rate of the IC can be adjusted through the use of thermal effects.
1. A test board for testing devices, comprising:
first and second communication ports configured for communication with a master device and a DUT, respectively;
a bit error rate tester arranged for communication with the master device and with the DUT by way of the first and second communication ports, respectively, and the bit error rate tester including at least one IC whose maximum data rate is temperature sensitive; and
a temperature control system arranged for thermal control of the IC of the bit error rate tester.
2. The test board as recited in claim 1 , wherein the at least one IC comprises a SERDES.
3. The test board as recited in claim 1 , wherein the test board is Fibre Channel compatible and is capable of operation at nominal data rates of 1.0625 Gb/s, 2.125 Gb/s, and 4.25 Gb/s.
4. The test board as recited in claim 1 , wherein test board is configured for use with a DUT and master device that are connected with each other in an immediate loop-back arrangement.
5. The test board as recited in claim 1 , further comprising a microcontroller and CPLD connected with each other, and wherein the temperature control system comprises:
a temperature control device connected with at least one of the microcontroller and the CPLD, and the temperature control device arranged for thermal communication with the IC; and
a temperature sensor connected with at least one of the microcontroller and the CPLD, and the temperature sensor arranged for thermal control of the IC.
6. The test board as recited in claim 5 , wherein the temperature control device comprises at least one of: a TEC; and, a fan.
7. The test board as recited in claim 5 , wherein the temperature control device is mounted on the IC.
8. The test board as recited in claim 1 , wherein the first and second communication ports are configured for communication with a master transceiver and a test transceiver, respectively.
9. A test board for testing devices, comprising:
first and second communication ports configured for communication with a master device and a DUT, respectively;
a bit error rate tester arranged for communication with the master device and with the DUT by way of the first and second communication ports, respectively, and the bit error rate tester including at least one IC whose maximum data rate is temperature sensitive; and
means for regulating temperature, the means for regulating temperature serving to substantially maintain the IC at a temperature that corresponds with a desired maximum data rate.
10. The test board as recited in claim 9 , wherein the means for regulating temperature brings the IC to the temperature that corresponds with the desired maximum data rate.
11. The test board as recited in claim 9 , wherein the means for regulating temperature cools or heats the IC as necessary to maintain the temperature that corresponds with the desired maximum data rate.
12. The test board as recited in claim 9 , wherein the means for regulating temperature adjusts the temperature of the IC based upon temperature information concerning the IC.
13. The test board as recited in claim 9 , wherein the means for regulating temperature adjusts the temperature of the IC as necessary to facilitate achievement of another desired maximum data rate.
14. The test board as recited in claim 9 , wherein the means for regulating temperature employs a thermoelectric cooling effect to maintain the temperature of the
IC.
15. The test board as recited in claim 9 , wherein the means for regulating temperature employs a closed-loop feedback method to maintain the temperature of the IC.