Generation of a frame synchronized clock for a wireless video receiver
An apparatus for receiving essentially uncompressed HDTV video must generate an accurate pixel-rate clock to enable the reconstruction of a video frame. The clock pixel-rate generated must match a received video pixel-rate. In such system, signals for generation of horizontal and vertical synchronization are not transmitted over the wireless link to conserve the use of bandwidth. In the invention, a start of frame (SOF) indication is extracted by a symbol detection and synchronization (SDS) module and is used to generate the pixel-rate clock.
1. A wireless video receiver to receive a wireless video transmission including data representing pixels of a video frame and a synchronization signal indicative of a beginning of said video frame, said wireless receiver comprising:
a clock generator to generate a pixel clock signal synchronized to said synchronization signal, wherein a clock rate of said pixel clock signal corresponds to a pixel rate of said pixels, said clock generator comprising:
a first clock generation module to generate an intermediate clock signal synchronized to said synchronization signal, wherein an intermediate clock rate of said intermediate clock signal is lower than said pixel rate; and
a second clock generation module to generate said pixel clock signal based on said intermediate clock signal.
2. The wireless video receiver of claim 1 , wherein the clock rate of said pixel clock signal is at least ten times greater than said intermediate clock rate.
3. The wireless video receiver of claim 1 , wherein the clock rate of said pixel clock signal is at least four orders of magnitude greater than said intermediate clock rate.
4. The wireless video receiver of claim 1 , wherein said first clock generation module comprises a digital phase-locked loop, and wherein said second clock generation module comprises an analog phase-locked loop.
5. The wireless video receiver of claim 1 , wherein said first clock generation module comprises:
a counter to generate said intermediate clock signal based on a value of said counter;
an offset register to maintain an offset value; and
an adder to add said offset value to the value of said counter at a system clock rate of a system clock of said receiver.
6. The wireless video receiver of claim 5 , wherein said clock generator is to adjust the offset value maintained by the offset register based on at least one of said intermediate clock signal and said pixel clock signal.
7. The wireless video receiver of claim 1 , wherein said wireless video receiver is capable of generating one or more video control signals based on said pixel clock signal, said video control signals comprising at least one of a horizontal-synchronization signal, a vertical synchronization signal, and a synchronization-on-green signal.
8. A wireless video communication system comprising:
a wireless video transmitter to transmit a wireless video transmission including data representing pixels of a video frame and a synchronization signal indicative of a beginning of said video frame; and
a wireless video receiver to receive said wireless video transmission, said receiver comprising a clock generator to generate a pixel clock signal synchronized to said synchronization signal, wherein a clock rate of said pixel clock signal corresponds to a pixel rate of said pixels,
wherein said clock generator comprises:
a first clock generation module to generate an intermediate clock signal synchronized to said synchronization signal, wherein an intermediate clock rate of said intermediate clock signal is lower than said pixel rate; and
a second clock generation module to generate said pixel clock signal based on said intermediate clock signal.
9. The wireless video communication system of claim 8 , wherein the clock rate of said pixel clock signal is at least ten times higher than said intermediate clock rate.
10. The wireless video communication system of claim 8 , wherein said first clock generation module comprises a digital phase-locked loop, and wherein said second clock generation module comprises an analog phase-locked loop.
11. The wireless video communication system of claim 8 , wherein said first clock generation module comprises:
a counter to generate said intermediate clock signal based on a value of said counter;
an offset register to maintain an offset value; and
an adder to add said offset value to the value of said counter at a system clock rate of a system clock of said receiver.
12. The wireless video communication system of claim 11 , wherein said clock generator is to adjust the offset value maintained by the offset register based on at least one of said intermediate clock signal and said pixel clock signal.
13. The wireless video communication system of claim 8 , wherein said wireless video receiver is capable of generating one or more video control signals based on said pixel clock signal, said video control signals comprising at least one of a horizontal-synchronization signal, a vertical synchronization signal, and a synchronization-on-green signal.
14. A method of wireless video communication, the method comprising:
receiving a wireless video transmission including data representing pixels of a video frame and a synchronization signal indicative of a beginning of said video frame; and
generating a pixel clock signal synchronized to said synchronization signal, wherein a clock rate of said pixel clock signal corresponds to a pixel rate of said pixels,
wherein generating said pixel clock comprises:
generating an intermediate clock signal synchronized to said synchronization signal, wherein an intermediate clock rate of said intermediate clock signal is lower than said pixel rate; and
generating said pixel clock signal based on said intermediate clock signal.
15. The method of claim 14 , wherein the clock rate of said pixel clock signal is at least ten times higher than said intermediate clock rate.
16. The method of claim 14 , wherein generating the intermediate clock signal comprises:
generating said intermediate clock signal based on a value of a counter;
maintaining an offset value; and
adding said offset value to the value of said counter at a system clock rate of a system clock.