Systems and methods for asynchronous triggering of an arbitrary waveform generator

1. A method for asynchronous triggering in a waveform generator, the method comprising:

generating a digital to analog converter (DAC) sample clock;

receiving a sequencer clock having a frequency of the DAC sample clock divided by an integer number N;

shifting a waveform data stream into an output data generator having an integer number I outputs each sequencer clock cycle;

multiplexing the I outputs of the output data generator into a single data stream and outputting the data stream to a DAC for conversion to an analog signal;

receiving an asynchronous trigger input signal;

splitting the asynchronous trigger input signal to generate a number M trigger inputs and delaying each of the trigger inputs after the asynchronous trigger input by:

starting with the first of the M trigger inputs, sequentially delaying each trigger input by an integer multiple of the DAC sample clock relative to the previous trigger input;

determining a trigger position by detecting the trigger input that is generated at the beginning of a next sequencer clock cycle; and

time-shifting the waveform data stream into the I-output data generator to output samples from an output corresponding to the trigger position.

2. The method of claim 1 where I=M=N.

3. The method of claim 2 where N=4.

4. The method of claim 1 further comprising:

latching a trigger latch word in a register at the first edge transition of the sequencer clock cycle following the edge transition of the asynchronous trigger.

5. The method of claim 4 further comprising:

analyzing the trigger latch word to determine the integer time-shifting needed to output the samples from the output.

6. An arbitrary waveform generator using the method of claim 1 to perform asynchronous triggering.

7. A system for asynchronous triggering in a waveform generator comprising:

a DAC sample clock for generating DAC sample clock signal;

a sequencer clock for generating a sequencer clock signal having a frequency of 1/N of the DAC sample clock;

an output data generator having I outputs to receive a waveform data stream of samples shifted into the data generator at the rate of the sequencer clock signal;

an output multiplexer coupled to receive samples from each of the I outputs of the output data generator and to output the samples as a multiplexed data stream to the DAC;

a triggering system to receive an asynchronous trigger and split the signal into an integer multiple M trigger inputs, each trigger input delayed by a DAC sample clock cycle; and

a shift controller to determine a trigger position based on the trigger inputs and to shift a different waveform data stream into the data generator in accordance with the trigger position.

8. The system of claim 7 where I=M=N.

9. The system of claim 8 where N=4.

10. The system of claim 7 further comprising:

a trigger latch to receive the M trigger inputs and to latch the M trigger input states at the next transition of the sequencer clock.

11. The system of claim 7 where the triggering system uses a double data rate register (DDR) and a doubled clock to split the asynchronous trigger and to delay the trigger inputs.

12. The system of claim 7 where the output data generator includes waveform memory containing waveform sample streams representing at least one analog signal waveform.

13. The system of claim 7 further comprising a waveform memory system containing waveform sample streams representing at least one analog signal waveform.

14. An asynchronous triggering system for use in a waveform generator comprising:

an asynchronous trigger input to receive an asynchronous signal;

digital logic to split the asynchronous signal into an integer multiple M trigger inputs, and to output each trigger signal sequentially, each trigger signal delayed by a delay time after the previous trigger signal; and

a tripper latch to receive the M trigger inputs and to latch a corresponding M tripper input states at a next transition of a sequencer clock.

15. A field programmable logic array device comprising circuitry for implementing the asynchronous triggering system of claim 14 .

16. A method for asynchronous triggering comprising:

receiving an asynchronous trigger input signal;

splitting the asynchronous trigger input signal to generate a number M trigger inputs and delaying each of the trigger inputs after the asynchronous trigger input by:

starting with the first of the M trigger inputs, sequentially delaying each trigger input by a delay relative to the previous trigger input; and

receiving the M trigger inputs at a register and latching a trigger latch word in the register at a first edge transition of a sequencer clock cycle following an edge transition of the asynchronous trigger input signal, the trigger latch word comprising M trigger input states.

17. The method of claim 16 further comprising:

analyzing the trigger latch word to determine a trigger position within the sequencer clock cycle at which to shift in the new waveform.

18. The method of claim 16 further comprising:

outputting the trigger latch word to a waveform generator having a sequencer clock, the trigger latch word indicative of a trigger position that may be used by the waveform generator to switch to another waveform, the switching occurring with a resolution that is less than a resolution of the sequencer clock cycle.