Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices
View Patent ↗Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).
1. A method, comprising:
for each non-zero sub-matrix in a row of a first LDPC (Low Density Parity Check) matrix that includes a plurality of sub-matrices, selecting a corresponding shift value that is less than at least one of a number of columns and a number of rows of each sub-matrix of the plurality of sub-matrices;
for every non-zero sub-matrix of the first LDPC matrix except those sub-matrices in the row, selecting a corresponding shift value such that the corresponding shift values corresponding to all of the plurality of sub-matrices of the first LDPC matrix corporately either:
induce cycles of a first predetermined size in a first LDPC bipartite graph of a first LDPC code that corresponds to the first LDPC matrix; or
induce no cycles smaller that a second predetermined size in the first LDPC bipartite graph of the first LDPC code that corresponds to the first LDPC matrix;
performing cyclic shifting according to the selected shift value corresponding to each non-zero sub-matrix of the first LDPC matrix thereby generating a plurality of CSI sub-matrices;
arranging the plurality of CSI sub-matrices and any all-zero-valued sub-matrix of the first LDPC matrix thereby generating a second LDPC matrix that corresponds to a second LDPC code; and
employing the second LDPC matrix when processing an LDPC coded signal.
2. The method of claim 1 , the employing the second LDPC matrix when processing the LDPC coded signal comprising:
forming a generator matrix that corresponds to the second LDPC matrix; and
encoding at least one information bit using the generator matrix thereby generating the LDPC coded signal.
3. The method of claim 1 , the employing the second LDPC matrix when processing the LDPC coded signal comprising:
encoding at least one information bit using the second LDPC matrix thereby generating the LDPC coded signal.
4. The method of claim 1 , the employing the second LDPC matrix when processing the LDPC coded signal comprising:
decoding the LDPC coded signal using the second LDPC matrix thereby generating a best estimate of at least one information bit encoded therein.
5. The method of claim 1 , wherein:
the selecting the corresponding shift value that is less than at least one of the number of columns and the number of rows of each sub-matrix of the plurality of sub-matrices involves randomly selecting.
6. The method of claim 1 , wherein:
the row of the first LDPC is the first row of the first LDPC matrix.
7. The method of claim 1 , wherein:
the selecting the corresponding shift value row is performed either randomly or according to a predetermined pattern.
8. The method of claim 1 , further comprising:
determining a number of cycles of a third predetermined size in a second LDPC bipartite graph of the second LDPC code that corresponds to the second LDPC matrix; and wherein:
the number of the cycles of the third predetermined size in the second LDPC bipartite graph is less than a predetermined number.
9. The method of claim 1 , further comprising:
arranging the plurality of CSI sub-matrices and any all-zero-valued sub-matrix of the first LDPC code thereby generating a third LDPC matrix that corresponds to a third LDPC code such that the arranging that generates the third LDPC matrix is different than the arranging the plurality of CSI sub-matrices and any all-zero-valued sub-matrix of the first LDPC code that results in the generating the second LDPC matrix that corresponds to the second LDPC code;
determining a first performance corresponding to the third LDPC code for coded signal transmission across a communication channel in terms of BER (Bit Error Rate) as a function of SNR (Signal to Noise Ratio);
determining a second performance corresponding to the second LDPC code for coded signal transmission across the communication channel in terms of BER as a function of SNR; and
processing the LDPC coded signal using the third LDPC matrix when the first performance has a lower BER as a function of SNR than the second performance.
10. An apparatus, comprising:
a processing module; and
a memory, coupled to the processing module, that is operable to store operational instructions that enable the processing module to:
for each non-zero sub-matrix in first row of a first LDPC (Low Density Parity Check) matrix that includes a plurality of sub-matrices, select a corresponding shift value that is less than at least one of a number of columns and a number of rows of each sub-matrix of the plurality of sub-matrices;
for every non-zero sub-matrix of the first LDPC matrix except those sub-matrices in the first row, select a corresponding shift value such that the corresponding shift values corresponding to all of the plurality of sub-matrices of the first LDPC matrix corporately either:
induce cycles of a first predetermined size in a first LDPC bipartite graph of a first LDPC code that corresponds to the first LDPC matrix; or
induce no cycles smaller that a second predetermined size in the first LDPC bipartite graph of the first LDPC code that corresponds to the first LDPC matrix;
perform cyclic shifting according to the selected shift value corresponding to each non-zero sub-matrix of the first LDPC matrix thereby generating a plurality of CSI sub-matrices;
arrange the plurality of CSI sub-matrices and any all-zero-valued sub-matrix of the first LDPC matrix thereby generating a second LDPC matrix that corresponds to a second LDPC code; and
employ the second LDPC matrix to process an LDPC coded signal.
11. The apparatus of claim 10 , wherein the memory, coupled to the processing module, is operable to store operational instructions that enable the processing module to:
arrange the plurality of CSI sub-matrices and any all-zero-valued sub-matrix of the first LDPC code thereby generating a third LDPC matrix that corresponds to a third LDPC code such that the arranging that generates the third LDPC matrix is different than the arranging the plurality of CSI sub-matrices and any all-zero-valued sub-matrix of the first LDPC code that results in the generating the second LDPC matrix that corresponds to the second LDPC code.
12. The apparatus of claim 10 , wherein the memory, coupled to the processing module, is operable to store operational instructions that enable the processing module to:
arrange the plurality of CSI sub-matrices and any all-zero-valued sub-matrix of the first LDPC code thereby generating a third LDPC matrix that corresponds to a third LDPC code such that the arrangement that generates the third LDPC matrix is different than the arrangement of the plurality of CSI sub-matrices and any all-zero-valued sub-matrix of the first LDPC code that results in the generating the second LDPC matrix that corresponds to the second LDPC code.
13. The apparatus of claim 10 , wherein:
the apparatus is an encoder that is operable to encode at least one information bit using a generator matrix that corresponds to the second LDPC matrix thereby generating the LDPC coded signal.
14. The apparatus of claim 10 , wherein:
the apparatus is an encoder that is operable to encode at least one information bit using the second LDPC matrix thereby generating the LDPC coded signal.
15. The apparatus of claim 10 , wherein:
the apparatus is a decoder that is operable to decode the LDPC coded signal using the second LDPC matrix thereby generating a best estimate of at least one information bit encoded therein.
16. A method, comprising:
for each non-zero sub-matrix in first row of a first LDPC (Low Density Parity Check) matrix that includes a plurality of sub-matrices, randomly selecting a corresponding shift value that is less than at least one of a number of columns and a number of rows of each sub-matrix of the plurality of sub-matrices;
for every non-zero sub-matrix of the first LDPC matrix except those sub-matrices in the first row, selecting a corresponding shift value such that the corresponding shift values corresponding to all of the plurality of sub-matrices of the first LDPC matrix corporately either:
induce cycles of a first predetermined size in a first LDPC bipartite graph of a first LDPC code that corresponds to the first LDPC matrix; or
induce no cycles smaller that a second predetermined size in the first LDPC bipartite graph of the first LDPC code that corresponds to the first LDPC matrix;
performing cyclic shifting according to the selected shift value corresponding to each non-zero sub-matrix of the first LDPC matrix thereby generating a plurality of CSI sub-matrices;
arranging the plurality of CSI sub-matrices and any all-zero-valued sub-matrix of the first LDPC matrix according to a first arrangement thereby generating a second LDPC matrix that corresponds to a second LDPC code;
arranging the plurality of CSI sub-matrices and any all-zero-valued sub-matrix of the first LDPC matrix according to a second arrangement thereby generating a third LDPC matrix that corresponds to a third LDPC code; and
employing the second LDPC matrix or the third LDPC matrix when processing an LDPC coded signal.
17. The method of claim 16 , wherein the employing the second LDPC matrix or the third LDPC matrix when processing the LDPC coded signal comprising:
encoding at least one information bit using the second LDPC matrix or the third LDPC matrix thereby generating the LDPC coded signal.
18. The method of claim 16 , wherein the employing the second LDPC matrix or the third LDPC matrix when processing the LDPC coded signal comprising:
decoding the LDPC coded signal using the second LDPC matrix or the third LDPC matrix thereby generating a best estimate of at least one information bit encoded therein.
19. The method of claim 16 , further comprising:
determining a number of cycles of a third predetermined size in a second LDPC bipartite graph of the second LDPC code that corresponds to the second LDPC matrix; and wherein:
the number of the cycles of the third predetermined size in the second LDPC bipartite graph is less than a predetermined number.
20. The method of claim 16 , further comprising:
determining a first performance corresponding to the third LDPC code for LDPC coded signal transmission across a communication channel in terms of BER (Bit Error Rate) as a function of SNR (Signal to Noise Ratio); and
determining a second performance corresponding to the second LDPC code for LDPC coded signal transmission across the communication channel in terms of BER as a function of SNR.