Semiconductor memory circuit
View Patent ↗The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
1. A semiconductor circuit apparatus, comprising:
a first input means for receiving a first power supply voltage and a first signal and outputting an internal signal;
a second input means for receiving the first power supply voltage and a control signal;
a first processing means for outputting a second signal in response to the control signal;
an output means for outputting an output signal based on the second signal; and
a power supply means for receiving the first power supply voltage and the internal signal, and for supplying an operation voltage to the first processing means,
wherein the first signal instructs a first mode which stops supplying the operation voltage from the power supply means to the first processing means, and
wherein the output means is brought to an output high impedance state in response to the internal signal in the first mode.
2. The semiconductor circuit apparatus according to claim 1 , wherein the first mode is a low power consumption mode.
3. The semiconductor circuit apparatus according to claim 1 , wherein the power supply means comprises:
an operation voltage generating circuit which supplies the operation voltage to the first processing means; and
a switch circuit which receives the first power supply voltage and supplies the first power supply voltage to the operation voltage generating circuit in response to the internal signal.
4. The semiconductor circuit apparatus according to claim 1 , wherein the first processing means comprises:
a memory array comprising a plurality of word lines, a plurality of data lines, a plurality of memory cells respectively connected to the plurality of word lines and the plurality of data lines; and
a word line drive circuit connected to the plurality of word lines, and
wherein the operation voltage is a voltage for driving the word line drive circuit.