Memory

1. A memory comprising:

an external access detection portion detecting an external access operation;

an access control portion performing an internal access operation on the basis of said external access operation; and

a refresh determination portion determining whether or not to perform a refresh operation on the basis of detection of said external access operation by said external access detection portion and the operating state of said access control portion, wherein

said access control portion performs said refresh operation before or after said internal access operation on the basis of the result of determination of said refresh determination portion.

2. The memory according to claim 1 , wherein

said refresh determination portion outputs a signal for performing said refresh operation if said access control portion performs neither said internal access operation nor said refresh operation when said external access detection portion detects said external access operation.

3. The memory according to claim 1 , wherein

said access control portion performs said internal access operation after completion of said refresh operation if performing said refresh operation when said external access detection portion detects said external access operation.

4. The memory according to claim 1 , wherein

said access control portion performs said internal access operation after completion of precedent said internal access operation if performing said precedent internal access operation when said external access detection portion detects said external access operation.

5. The memory according to claim 1 , wherein

said access control portion performs said internal access operation and thereafter performs no said refresh operation after completion of said internal operation or said refresh operation if performing either said internal access operation or said refresh operation when said external access detection portion detects said external access operation.

6. The memory according to claim 1 , wherein

the period of said internal access operation is shorter than the period of said external access operation.

7. The memory according to claim 1 , further comprising an external access counting portion counting the access frequency of said external access operation, wherein

said access control portion performs said refresh operation on the basis of the result of determination of said refresh determination portion and the access frequency counted by said external access counting portion.

8. The memory according to claim 1 , wherein

said internal access operation includes a data read operation and a data rewrite operation as well as a data write operation, and

said refresh operation includes a data read operation and a data rewrite operation.

9. The memory according to claim 1 , further comprising:

a word line and a bit line arranged to intersect with each other, and

a memory cell arranged to be linked to at least said word line, wherein

said access control portion collectively performs said refresh operation every said word line on said memory cell linked to said word line.

10. The memory according to claim 1 , further comprising:

a word line and a bit line arranged to intersect with each other, and

a ferroelectric capacitor arranged between said word line and said bit line.

11. The memory according to claim 1 , further comprising a switching portion switching a row address signal corresponding to an internal address signal for performing said internal access operation and another row address signal corresponding to a refresh address signal for performing said refresh operation.

12. The memory according to claim 2 , wherein

said access control portion performs said internal access operation and thereafter continuously performs said refresh operation on the basis of said signal for performing said refresh operation if performing neither said internal access operation nor said refresh operation when said external access detection portion detects said external access operation.

13. The memory according to claim 6 , wherein

said access control portion includes a clock generation portion generating an internal clock having a cycle shorter than the period of said external access operation,

for performing each of said internal access operation and said refresh operation in one cycle of said internal clock.

14. The memory according to claim 13 , wherein

said external access operation is non-cyclically performed,

said internal clock includes an internal clock for said internal access operation and an internal clock for said refresh operation, and

said access control portion performs said refresh operation in the period of next said external access operation if the period of said external access operation is not less than the sum of the cycle of said internal clock for said internal access operation and the cycle of said internal clock for said refresh operation.

15. The memory according to claim 13 , wherein

said external access operation is cyclically performed,

said internal clock includes an internal clock for said internal access operation and an internal clock for said refresh operation, and

the period of said external access operation is shorter than the sum of the cycle of said internal clock for said internal access operation and the cycle of said internal clock for said refresh operation.

16. The memory according to claim 15 , wherein

said access control portion performs said refresh operation once every plurality of times of said internal access operation.