Electrostatic discharge protection structures for high speed technologies with mixed and ultra-low voltage supplies
View Patent ↗An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry is provided herein. In one embodiment, a circuit for protecting an integrated circuit from ESD includes a protected circuit node in the integrated circuit, a multiple stage transistor pump circuit coupled to the protected circuit node, and an electrostatic discharge protection circuit having a trigger coupled to the multiple stage transistor pump circuit. The multiple stage transistor pump circuit may comprise a Darlington transistor pump circuit.
1. A circuit for protecting an integrated circuit from electrostatic discharge, comprising:
a protected circuit node in the integrated circuit;
a silicon controlled rectifier in electrical communication with the protected circuit node and a ground, the silicon controlled rectifier having first and second trigger gates, wherein said first trigger gate comprise a base of a npn transistor and second trigger gate comprise a base of a pnp transistor; and
a plurality of serially-coupled trigger diodes having first and second ends in electrical communication with the first and second trigger gates, respectively, wherein each of the plurality of serially-coupled trigger diodes is biased in a forward conduction direction from the second trigger gate to the first trigger gate.
2. The circuit of claim 1 , further comprising: at least one resistor in electrical communication from between the first trigger gate and the ground.
3. The circuit of claim 1 further comprising at least one resistor in electrical communication between the second trigger gate and the protected circuit node.
4. The circuit of claim 1 wherein said diodes are PN junction diodes coupled to base of the NPN bipolar transistor.
5. The circuit of claim 1 further comprising at least one capacitor coupled in series between the diodes and the ground.