Organic light emitting display device and method of fabricating the same
View Patent ↗Provided are an organic light emitting display device (OLED) and a method of fabricating the same. When a electrically conductive line and a gate electrode are formed at the same time or when a first electrode is formed, interconnections for electrically connecting elements are formed. Thus, the number of used masks can be reduced, so that the overall fabrication process can be shortened and the production cost can be reduced.
1. An organic light emitting display device, comprising:
a substrate;
a first thin film transistor formed over the substrate;
an electrically conductive line formed over the substrate, wherein the electrically conductive line is configured to provide power to the first thin film transistor;
a planarization layer formed over the first thin film transistor and the electrically conductive line;
a pixel electrode formed on and contacting the planarization layer;
an organic light emitting layer formed over the pixel electrode; and
a first interconnection electrically interconnecting the electrically conductive line and the first thin film transistor, wherein the first interconnection comprises:
a first portion formed on and contacting the planarization layer,
a second portion connecting the first portion and the electrically conductive line through the planarization layer, and
a third portion connecting the first portion and a part of the first thin film transistor,
wherein the first thin film transistor comprises a source, a drain and a channel located therebetween,
wherein the electrically conductive line is located below the source, the drain and the channel, and
wherein the pixel electrode is formed of a material and the first interconnection is formed of the material.
2. The device of claim 1 , wherein the part of the first thin film transistor comprises the source or the drain.
3. The device of claim 1 , wherein the first thin film transistor comprises a gate electrode, and wherein the electrically conductive line is formed simultaneously with the gate electrode.
4. The device of claim 1 , further comprising a second thin film transistor formed between the substrate and the planarization layer.
5. The device of claim 4 , wherein the first thin film transistor comprises an NMOS transistor, and wherein the second thin film transistor comprises a PMOS transistor.
6. The device of claim 4 , further comprising a second interconnection electrically interconnecting the first thin film transistor and the second thin film transistor, wherein the second interconnection comprises:
a first portion formed over the planarization,
a second portion connecting the first portion and the first thin film transistor through the planarization layer, and
a third portion connecting the first portion and the second thin film transistor.
7. The device of claim 4 , further comprising a second interconnection, wherein the second interconnection electrically interconnects the pixel electrode and the first or second thin film transistor, the second interconnection comprising a portion formed through the planarization layer.
8. The device of claim 7 , wherein the second interconnection comprises a material, and wherein the pixel electrode comprises the same material.
9. The device of claim 7 , wherein the pixel electrode and the second interconnection are continuous.
10. The device of claim 7 , wherein the second interconnection comprises a first layer comprising a first material and a second layer comprising a second material, and wherein the pixel electrode comprises a first layer comprising the first material and a second layer comprising the second material.
11. The device of claim 10 , wherein the first material comprises one or more selected from the group consisting of Al, Ag, an Al alloy, and an Ag alloy.
12. The device of claim 10 , wherein the second material comprises ITO or IZO.
13. The device of claim 1 , wherein the pixel electrode comprises an extended surface, substantially the entire extended surface being formed on and contacting the planarization layer.
14. The device of claim 1 , wherein the first thin film transistor comprises a gate electrode formed over the substrate, and the part of the first thin film transistor is formed on a layer over the electrically conductive line.