Low-speed DLL employing a digital phase interpolator based upon a high-speed clock
View Patent ↗A low-speed DLL facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected. The phase chosen is that which eliminates any difference in the phases of the 156 MHz clock that clocks the data transmitted to the ASIC domain and the clock that is used in the ASIC domain to latch the data. Thus, the interpolator takes advantage of the availability of the high-speed clock to generate a sufficient number of phases for a low speed DLL.
1. A digital interpolator comprising:
a shift register comprising a plurality of flip-flops each having a Q output and a data input, the plurality of flip-flops coupled in series with the Q output of each shift register coupled to the data input of a next flip-flop in the series, the Q output of a last flip flop in the series being coupled to the data input of a first of the flip-flops in the series;
a multiplexer having a plurality of inputs coupled to receive the plurality of Q outputs of the flip-flops, and having an output that produces one of the inputs based on a k-bit select input, where k is an integer and the plurality of inputs is equal to 2 k ;
wherein the plurality of flip-flops is clocked by a high speed clock having a first frequency to produce a plurality of phases of a first low-speed clock having a second frequency that is substantially lower than the first frequency; and
wherein a single binary bit is recirculated through the shift register to produce the positive going edge of each phase of the first low-speed clock.
2. The digital interpolator of claim 1 wherein:
the high speed clock is divided down by 2 n to produce a second low speed clock at the second frequency;
the flip-flops are sensitive to both edges of the first high-speed clock; and
the shift register comprises 2(2 n ) flip-flops producing 2(2 n ) phases of the first low-speed clock.
3. The digital interpolator of claim 2 wherein one of the 2(2 n ) phases of the first low-speed clock is selected based on a phase difference between the first and the second low-speed clock translated to a k bit value.
4. The digital interpolator of claim 1 wherein one of the 2(2 n ) phases of the first low-speed clock is selected based on a phase difference between the first and the second low-speed clock translated to a k bit value.