Package frame and semiconductor package using the same
View Patent ↗Provided are a lead frame and a semiconductor package which allows reliable attachment of a small-sized semiconductor chip requiring a large number of leads to a board while providing high heat dissipation capability. The semiconductor package includes leads, each having a top plate extending inward from the outside edge of a frame and a plurality of pillar-shaped portions supporting the top plates, a semiconductor chip attached onto edge portions of the leads, wires connecting the leads with corresponding bonding pad on the semiconductor chip, and a molding material encapsulating the semiconductor chip and the wires and parts of the leads so as to the bottom surfaces of the leads are exposed. Further, some embodiments have a conductive pad exhibiting higher heat dissipation.
1. A packaged semiconductor comprising:
a plurality of first conductive leads, each including first and second pillar-shaped portions and a top plate covering the tops of the first and second pillar-shaped portions, which are spaced apart from one another and arranged such that the second pillar-shaped portions face inward, wherein the lateral length of the top plate is greater than the corresponding lateral length of one of the first and second pillar shaped portions;
a semiconductor chip having a top surface on which a plurality of bonding pads are disposed and edge portions attached onto edges of top plates of the first conductive leads;
a plurality of first conductive wires connecting at least some of the bonding pads on the semiconductor chip with corresponding ones of the first conductive leads;
a molding material encapsulating the semiconductor chip and the first conductive wires and parts of the first conductive leads so as to expose at least bottom surfaces of the first and second pillar-shaped portions of the first conductive leads the packaged semiconductor further comprising:
a plurality of second conductive leads, each including respective first, second, and third pillar-shaped portions and a top plate covering the first, second, and third pillar-shaped portions, which are spaced apart from and arranged alternately with the first conductive; and
a plurality of second conductive wires connecting at least some of the bonding pads on the semiconductor chip with corresponding ones of the second conductive leads;
wherein the molding material further encapsulates portions of the second conductive leads so as to expose the bottom surfaces of plurality of second conductive leads, wherein the edge portions of the semiconductor chip are attached onto edge portions of the top plates of the second conductive leads.
2. The packaged semiconductor of claim 1 , wherein the edge portions of the semiconductor chip are attached onto the top plates on the second pillar-shaped portions of the first conductive leads.
3. The packaged semiconductor of claim 2 , wherein the molding material encapsulates a gap between the first and second pillar-shaped portions of the first conductive leads.
4. The packaged semiconductor of claim 2 , wherein the molding material further exposes at least one side of the first pillar-shaped portion of each of the first conductive leads.
5. The packaged semiconductor of claim 1 , further comprising a conductive pad attached onto a central portion of a bottom surface of the semiconductor chip and disposed at a central portion inside the first conductive leads, wherein the molding material further encapsulates a portion of the conductive pad so as to expose the bottom surface of the conductive pad.
6. The packaged semiconductor of claim 5 , wherein the conductive pad connects with top plates of at least one pair of the first conductive leads.
7. The packaged semiconductor of claim 1 , wherein the edge portions of the semiconductor chip are further attached onto the top plates on the third pillar-shaped portions of the second conductive leads.
8. A packaged semiconductor comprising:
a plurality of first conductive leads, each including spaced-apart first and second pillar-shaped portions and a top plate covering the first and second pillar-shaped portions, which are spaced apart from one another and arranged such that the second pillar-shaped portions face inward;
a plurality of second conductive leads, each including a first, second, and third pillar-shaped portions and a top plate covering the first, second, and third pillar-shaped portions, which are spaced apart from and arranged alternately with the first conductive leads;
a semiconductor chip having a top surface on which a plurality of bonding pads are disposed and edge portions attached onto at least edges of top plates of the first conductive leads;
a plurality of conductive wires connecting the bonding pads on the semiconductor chip with corresponding ones of the first and second conductive leads;
a molding material encapsulating the semiconductor chip and the plurality of conductive wires and parts of the first and second conductive leads so as to expose at least bottom surfaces of the first and second pillar-shaped portions of the first conductive leads and the second conductive leads the packaged semiconductor further comprising a conductive pad attached beneath a bottom surface of the semiconductor chip and disposed at a central portion inside the first and second conductive leads,
wherein the molding material further encapsulates a portion of the conductive pad so as to expose the bottom surface of the conductive pad, wherein the conductive pad connects with top plates of at least one pair of the first conductive leads.
9. The packaged semiconductor of claim 8 , wherein the edge portions of the semiconductor chip are attached onto the top plates on the second pillar-shaped portions of the first conductive leads.
10. The packaged semiconductor of claim 9 , wherein the edge portions of the semiconductor chip are further attached onto the top plates of the second conductive leads.
11. The packaged semiconductor of claim 8 , wherein the conductive pad connects with top plates of at least one pair of the second conductive leads.
12. A lead frame for a packaged semiconductor, comprising:
a plurality of half-etched first conductive leads, each including first and second pillar-shaped portions and a top plate covering at least the first and second pillar-shaped portions, which are spaced apart from one another and arranged such that the second pillar-shaped portions face inward;
a plurality of second conductive leads, each including respective first, second, and third pillar-shaped portion portions and a top plate covering the first, second and third pillar-shaped which are spaced apart from and arranged alternately with the first conductive leads;
a conductive pad disposed on a central portion of the frame inside the first conductive leads, and
wherein the conductive pad connects with the top plates of at least one pair of the first conductive leads.
13. The lead frame of claim 12 , further comprising the conductive pad disposed on a central portion of the frame inside the second conductive leads, and
wherein the conductive pad connects with the top plates of at least one pair of the second conductive leads.