IP Library Granted Patent US 8,222,672
Granted Patent B2
US 8,222,672 · App. 11/476,205 · Granted Jul 17, 2012

Semiconductor device and manufacturing method thereof

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Quick Facts
Patent No.
US 8,222,672
App. No.
11/476,205
Granted
Jul 17, 2012
Kind
B2
Abstract

A semiconductor device is configured so as to comprise a substrate, an n-type semiconductor layer or an undoped semiconductor layer on the substrate, and an ohmic electrode on the n-type semiconductor layer or the undoped semiconductor layer, and the ohmic electrode is configured so as to comprise a tantalum layer formed on the n-type semiconductor layer or the undoped semiconductor layer, an aluminum layer formed on the tantalum layer, and a metal layer formed on the aluminum layer and made of any one material of tantalum, nickel, palladium, and molybdenum.

Claims (33)

1. A semiconductor device comprising:

a substrate;

an n-type nitride semiconductor layer or an undoped nitride semiconductor layer over the substrate; and

a source electrode and a drain electrode being in direct physical contact with and being in ohmic contact with said n-type nitride semiconductor layer or said undoped nitride semiconductor layer;

wherein each of said source electrode and said drain electrode comprises:

a tantalum layer formed on said n-type nitride semiconductor layer or said undoped nitride semiconductor layer;

an aluminum layer formed on said tantalum layer and made of aluminum only; and

a metal layer formed on said aluminum layer and made of any one material of tantalum, nickel and palladium;

further comprising a compound layer of aluminum and any one material of tantalum, nickel and palladium between said aluminum layer and said metal layer; and

a gate electrode comprising a nickel layer and a gold layer formed on the nickel layer.

2. The semiconductor device according to claim 1 , wherein said n-type nitride semiconductor layer or said undoped nitride semiconductor layer is a III-V group nitride compound semiconductor layer.

3. The semiconductor device according to claim 1 , further comprising an Al x Ga 1-x N (0≦x≦1) layer as said n-type nitride semiconductor layer or said undoped nitride semiconductor layer, and being a field effect transistor having a gate electrode.

4. The semiconductor device according to claim 3 ,

further comprising:

a GaN electron transit layer formed below said Al x Ga 1-x N (0≦x≦1) electron supply layer; and

a GaN layer formed between said gate electrode and said Al x Ga 1-x N (0≦x≦1) electron supply layer;

wherein said Al x Ga 1-x N (0≦x≦1) layer is an Al x Ga 1-x N (0≦x≦1) electron supply layer.

5. The semiconductor device according to claim 4 , wherein said GaN layer is doped with n-type impurity materials of 1×10 17 cm −3 or more.

6. The semiconductor device according to claim 4 , wherein said GaN layer is formed below said source electrode and said drain electrode,

wherein said GaN layer is thinner in thickness at a portion below said source electrode and said drain electrode than at a portion below said gate electrode.

7. The semiconductor device according to claim 4 , wherein said Al x Ga 1-x N (0≦x≦1) electron supply layer is thinner in thickness at a portion below said source electrode and said drain electrode than at a portion below said gate electrode.

8. The semiconductor device according to claim 1 , wherein said substrate is a silicon carbide substrate having a resistivity of 1×10 6 Ω·cm or more.

9. The semiconductor device according to claim 1 , wherein said substrate is a conductive substrate having a resistivity of 1×10 5 Ω·cm or less.

10. A semiconductor device comprising:

a substrate;

an n-type nitride semiconductor layer or an undoped nitride semiconductor layer over the substrate; and

a source electrode and a drain electrode being in direct physical contact with and being in ohmic contact with said n-type nitride semiconductor layer or said undoped nitride semiconductor layer;

wherein each of said source electrode and said drain electrode comprises:

a first tantalum layer formed on said n-type nitride semiconductor layer or said undoped nitride semiconductor layer;

an aluminum layer formed on said first tantalum layer and made of aluminum only; and

a second tantalum layer formed on said aluminum layer;

further comprising a compound layer of aluminum and tantalum between said aluminum layer and said second tantalum layer; and

a gate electrode comprising a nickel layer and a gold layer formed on the nickel layer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2023
From: FUJITSU LIMITED
To: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
Reel/Frame 062784/0627 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY DATA, PREVIOUSLY RECORDED ON REEL 018272 FRAME 0097. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNOR'S INTEREST. Recorded Jan 3, 2012
From: KANAMURA, MASAHITO; NISHI, MASAHIRO
To: FUJITSU LIMITED; EUDYNA DEVICES INC.
Reel/Frame 027472/0468 →
CHANGE OF NAME Recorded May 2, 2011
From: EUDYNA DEVICES, INC.
To: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
Reel/Frame 026214/0341 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2006
From: KANAMURA, MASAHITO; NISHI, MASAHIRO
To: FUJITSU LIMITED
Reel/Frame 018272/0097 →