IP Library Granted Patent US 7,724,831
Granted Patent B2
US 7,724,831 · App. 11/477,129 · Granted May 25, 2010

Method and apparatus for detection of load impedance modulation in a transformer circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,724,831
App. No.
11/477,129
Granted
May 25, 2010
Kind
B2
Abstract

A method and apparatus for detection of load impedance modulation as a result of communication of data from the secondary to the primary side of a transformer are presented. The load impedance on the secondary of the transformer barrier is modulated differentially using data to be communicated across the barrier. A detection circuit on the primary side isolates the load current from the magnetizing current in the primary. The load current is subsequently integrated over two consecutive Manchester periods and the integrated value from the first Manchester period is compared against that of the second period thereby recovering the receive data.

Claims (72)

1. An apparatus for detecting load impedance in a transformer comprising:

a transformer having a primary side and a secondary side, said transformer having a total current being sourced on said primary side, wherein said total current comprises a magnetizing inductance current component and a load current component;

a first circuit component coupled to said secondary side of said transformer, said first circuit component differentially modulating load impedance on said secondary side of said transformer, wherein said differentially modulating said load impedance comprises:

obtaining a data stream for communication from said secondary side to said primary side of said transformer;

using a Manchester encoder to convert said data stream to a differential receive bitstream; and

modulating said load impedance on said secondary side using said differential receive bitstream; and

a second circuit coupled to said primary side of said transformer for detection of said modulated load impedance by differentially integrating said load current on said primary side of said transformer.

2. The apparatus of claim 1 , wherein said load current is isolated from said total current by canceling said magnetizing current.

3. The apparatus of claim 1 , wherein said differentially integrating said load current comprises:

a circuit measuring an output of a voltage driver on said primary side, wherein said output is a voltage equivalent of absolute value of said load current;

a circuit generating an error signal between said load current and an average of said load current;

a circuit generating an integrated output voltage by integrating said error signal; and

a circuit comparing said integrated output signal to a fixed value at specific time intervals to generate discrete values corresponding to said load impedance modulation.

4. The apparatus of claim 3 , wherein said generating an error signal comprises:

a first voltage to current convener converting said voltage equivalent to said load current;

a filter circuit generating an average of said equivalent voltage;

a second voltage to current converter converting said average equivalent voltage to said average load current; and

a summer circuit generating said error signal by subtracting said average of said load current from said load current.

5. A method for detecting load impedance in a transformer comprising:

sourcing a total current on a primary side of a transformer, said transformer additionally having a secondary side, wherein said total current comprises a magnetizing inductance current component and a load current component;

modulating load impedance on said secondary side of said transformer using differential coding of data through a first circuit component coupled to said secondary side of said transformer, wherein said modulating said load impedance using said differential coding of data comprises:

obtaining a data stream for communication from said secondary side to said primary side of said transformer;

using a Manchester encoder to convert said data stream to a differential receive bitstream; and

modulating said load impedance on said secondary side using said differential receive bitstream; and

detecting said load impedance by differentially integrating said load current on said primary side of said transformer using a second circuit coupled to said primary side of said transformer.

6. The method of claim 5 , wherein said load current is isolated from said total current by canceling said magnetizing current.

7. The method of claim 5 , wherein said differentially integrating said load current comprises:

measuring an output of a voltage driver on said primary side, wherein said output is a voltage equivalent of absolute value of said load current;

generating an error signal between said load current and an average of said load current;

generating an integrated output voltage by integrating said error signal; and

comparing said integrated output signal to a fixed value at specific time intervals to generate discrete values corresponding to said load impedance modulation.

8. The method of claim 7 , wherein said generating an error signal comprises:

converting said voltage equivalent to said load current;

generating an average of said equivalent voltage;

converting said average equivalent voltage to said average load current; and

generating said error signal by subtracting said average of said load current from said load current.

9. An apparatus for detecting load impedance in a transformer comprising:

a transformer having a primary side and a secondary side;

a first circuit component coupled to said secondary side of said transformer, said first circuit component differentially modulating load impedance on said secondary side of said transformer, wherein said differentially modulating said load impedance comprises:

obtaining a data stream for communication from said secondary side to said primary side of said transformer;

using a Manchester encoder to convert said data stream to a differential receive bitstream; and

modulating said load impedance on said secondary side using said differential receive bitstream; and

a second circuit coupled to said primary side of said transformer for detection of said load impedance, wherein said second circuit differentially integrates load current on said primary side of said transformer for determination of said load impedance.

10. The apparatus of claim 9 , wherein said load current is isolated by canceling a magnetizing current component from total current on said primary side.

11. The apparatus of claim 9 , wherein said differentially integrating said load current comprises:

a circuit measuring an output of a voltage driver on said primary side, wherein said output is a voltage equivalent of absolute value of said load current;

a circuit generating an error signal between said load current and an average of said load current;

a circuit generating an integrated output voltage by integrating said error signal; and

a circuit comparing said integrated output signal to a fixed value at specific time intervals to generate discrete values corresponding to said load impedance modulation.

12. The apparatus of claim 11 , wherein said generating an error signal comprises:

a first voltage to current converter converting said voltage equivalent to said load current;

a filter circuit generating an average of said equivalent voltage;

a second voltage to current converter converting said average equivalent voltage to said average load current; and

a summer circuit generating said error signal by subtracting said average of said load current from said load current.

13. An apparatus for detecting impedance modulation comprising:

a current sense circuit coupled to a voltage driver that supplies a load current to a variable impedance, said current sense circuit providing a detection input signal proportional to the magnitude of said load current;

a threshold circuit sampling said detection input signal at a first sample point to obtain a first sample value associated with a first magnitude value of said load current and at a second sample point to obtain a second sample value associated with a second magnitude value of said load current, said threshold circuit comprising an averaging circuit that receives said first sample value and said second sample value and provides a threshold value; and

a decision circuit receiving said detection input signal and said threshold value and providing an output data signal, wherein said decision circuit comprises:

a subtraction circuit receiving said threshold value and said detection input signal and providing a difference output; and

an integrator integrating said difference output, said integrator being reset at the beginning of each bit period.

14. The apparatus of claim 13 , wherein said decision circuit is configured to sample said detection input signal adjacent to an endpoint of a Manchester period associated with an output data stream of said voltage driver.

15. The apparatus of claim 13 , wherein an impedance modulated data stream in said load current is Manchester encoded, and wherein said first sample point and said second sample point lie within the same bit period.

16. The apparatus of claim 13 , wherein said integrator is configured to switch a polarity of integration at a midpoint of said bit period.

17. A method for detecting impedance modulation in a communication circuit having a voltage driver that drives a voltage signal onto a variable load impedance, wherein said voltage signal embodies a transmit data stream and said variable load impedance is modulated with a receive data stream that is Manchester encoded, said method comprising:

sensing a load current in said voltage driver to provide a detection signal proportional to a magnitude of said load current;

integrating said detection signal over a bit period of said receive data stream to provide an integration result;

switching a polarity of said integration at a midpoint of said bit period; and

determining a binary result based on a polarity of said integration result at the end of said bit period.

18. The method of claim 17 , further comprising:

sampling said detection signal during a first half of said bit period and a second half of said bit period to provide a first value and a second value;

averaging said first value and said second value to provide an average signal; and

subtracting said average signal from said detection signal prior to said integration.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 6, 2010
From: TERIDIAN SEMICONDUCTOR HOLDINGS CORPORATION
To: MAXIM INTEGRATED PRODUCTS, INC.
Reel/Frame 024630/0620 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR AND ASSIGNEE PREVIOUSLY RECORDED ON REEL 024474 FRAME 0569. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR IS TERIDIAN SEMICONDUCTOR CORPORATION AND ASSIGNEE IS TERIDIAN SEMICONDUCTOR HOLDINGS CORPORATION. Recorded Jun 25, 2010
From: TERIDIAN SEMICONDUCTOR CORPORATION
To: TERIDIAN SEMICONDUCTOR HOLDINGS CORPORATION
Reel/Frame 024588/0664 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR ON THE NOTICE OF RECORDATION PREVIOUSLY RECORDED ON REEL 024474 FRAME 0569. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT ASSIGNOR IS TERIDIAN SEMICONDUCTOR HOLDINGS CORPORATION. Recorded Jun 24, 2010
From: TERIDIAN SEMICONDUCTOR HOLDINGS CORPORATION
To: MAXIM INTEGRATED PRODUCTS, INC.
Reel/Frame 024588/0146 →
MERGER Recorded Jun 3, 2010
From: TERIDIAN SEMICONDUCTOR CORPORATION
To: MAXIM INTEGRATED PRODUCTS, INC.
Reel/Frame 024474/0569 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2006
From: FUKAHORI, KIYOSHI; HERSHBARGER, RUSSELL
To: TERIDIAN SEMICONDUCTOR CORPORATION
Reel/Frame 018340/0010 →