Substrate bias feedback scheme to reduce chip leakage power
View Patent ↗Disclosed is an improved substrate bias feedback circuit, and a method for operating the same.
1. A method for determining a bias voltage, comprising:
converting a reference voltage to a reference current;
comparing the reference current to a baseline leakage current; and
generating a reverse bias voltage based upon the comparison of reference current to the baseline leakage current,
where the step of converting a reference voltage to a reference current comprises providing a reference voltage to a first operational amplifier and providing the output of the operational amplifier to the gate of a bias transistor and to the gate of a source transistor.
2. The method of claim 1 , where the step of comparing the reference current to a baseline voltage current comprises driving a voltage at the drain of the source transistor to a voltage power level due to an operational amplifier action of a second operational amplifier.
3. The method of claim 2 , wherein the step of generating a reverse bias voltage comprises increasing an output voltage of a second operational amplifier when a leakage current through a baseline circuit is higher than the reference current.
4. The method of claim 1 , wherein the step of generating a reverse bias voltage comprises increasing a voltage provided to a charge pump.
5. A method for determining a bias voltage, comprising:
converting a reference voltage to a reference current;
comparing the reference current to a baseline leakage current; and
generating a reverse bias voltage based upon the comparison of reference current to the baseline leakage current,
where the step of converting a reference voltage to a reference current comprises providing a reference voltage to a negative input of a first operational amplifier having a positive input coupled to the drain of a bias transistor, and providing the output of the first operational amplifier to the gate of a source transistor.
6. A substrate bias feedback circuit, comprising:
an operational amplifier block having a plurality of inputs and an voltage control output;
a charge pump block having an input coupled to the voltage control output of the operational amplifier block, and having a substrate voltage output;
a clamp block having a clock enable output coupled to the charge pump system and a reference voltage input; and
a baseline transistor having its a substrate bias coupled to the voltage output of the charge pump block.
7. The circuit of claim 6 , wherein the operational amplifier block further comprises a first operational amplifier having a negative terminal coupled to the reference voltage input, and a positive terminal coupled to a drain of a bias transistor.
8. The circuit of claim 7 wherein the operational amplifier block further comprises a p-type source transistor having a gate coupled to the output of the first operational amplifier, a source coupled to power and a drain coupled to the drain of the baseline transistor.
9. The circuit of claim 8 wherein the operational amplifier block further comprises a second operational amplifier having a negative terminal coupled to the drain of the p-type source transistor and a positive terminal coupled to internal chip power supply, and a voltage control output signal.
10. The circuit of claim 8 wherein the charge pump block comprises an analog clock driver having a clock enable input coupled to the clamp block and having an input coupled to the voltage control output of the second operational amplifier, and having a first and second output from a first and second branch of the analog clock driver circuit.
11. The circuit of claim 10 , wherein the charge pump block further comprises a charge pump cell having inputs coupled to the first and second output of the analog clock driver, and having an output substrate control voltage.
12. The circuit of claim 11 , wherein the baseline transistor comprises an n-type transistor, and wherein the gate of the n-type transistor is coupled to a ground voltage.
13. The circuit of claim 8 wherein the operational amplifier block further comprises a second operational amplifier having a positive terminal coupled to the drain of the p-type source transistor and a negative terminal coupled to internal chip power supply, and a voltage control output signal.
14. The circuit of claim 13 wherein the baseline transistor comprises a p-type transistor, and wherein the gate of the p-type transistor is coupled to a drain of the source transistor.
15. A circuit for determining a bias voltage, comprising:
an operational amplifier means having a voltage control means;
a charge pump means coupled to the voltage control means;
a clamp means having a clock enable output coupled to the charge pump means and a reference means; and
a baseline means having a substrate bias coupled to the charge pump means.
16. The circuit of claim 15 , wherein the operational amplifier is configurable to convert a reference voltage to a reference current.
17. The circuit of claim 15 , wherein the charge pump means is configurable to provide a reverse bias body voltage to the baseline means.
18. The circuit of claim 17 , wherein the clamp means is configurable to limit a max reverse body bias voltage.
19. The circuit of claim 15 , wherein the baseline means is configurable to control a leakage current.