Watermarking a chip design based on frequency of geometric structures
View Patent ↗A method for watermarking a circuit design layout based on frequency or number of geometric structures. The method includes dividing a circuit design layout into a plurality of segments or tiles. Certain segments are selected, and within these selected segments, a router alters the number of geometric structures, such as vias and jogs, of the circuit design layout in the selected segments to form the watermark without relying on a netlist. The number of geometric structures is changed slightly so that a random sampling of segments would not identify the watermark since the variations would not be detectable or would be within acceptable variances, but the watermark would be readily identified if the selected segments are known. The watermark or portions thereof can be used to encode one or more data bits.
1. A computer implemented method for watermarking a circuit design layout, comprising:
dividing a circuit design layout into a plurality of segments;
selecting one or more segments from the plurality of segments; and
generating a watermark in the circuit design layout by altering, using a routing machine that comprises at least one processor, the number of geometric structures of the circuit design layout in the one or more segments that are selected.
2. The computer implemented method of claim 1 , wherein the selected segments are randomly distributed.
3. The computer implemented method of claim 1 , wherein the number of vias is altered to generate the watermark.
4. The computer implemented method of claim 1 , wherein the number of jogs is altered to generate the watermark.
5. The computer implemented method of claim 1 , wherein the number of vias and the number of jogs are altered to generate the watermark.
6. The computer implemented method of claim 1 , wherein the number of geometric structures in the selected segments is altered by about 1-10% compared to the number of geometric structures in unselected segments.
7. The computer implemented method of claim 1 , wherein the number of geometric structures in the selected segments is less than the number of geometric structures in unselected segments.
8. The computer implemented method of claim 1 , wherein the number of geometric structures in the selected segments is greater than the number of geometric structures in unselected segments.
9. The computer implemented method of claim 1 , wherein generating the watermark comprises modifying routing of the circuit design layout in each selected segments to alter the number of geometric structures in each selected segment.
10. The computer implemented method of claim 1 , wherein all of the plurality of segments are the same shape.
11. The computer implemented method of claim 1 , wherein the plurality of segments are squares, rectangles, triangles or a combination of two or more thereof.
12. The computer implemented method of claim 1 , wherein the watermark is generated by selected segments that are grouped together.
13. The computer implemented method of claim 1 , wherein the watermark is generated by selected segments that are separated from each other.
14. The computer implemented method of claim 1 , wherein the watermark encodes a bit of data.
15. The computer implemented method of claim 1 , wherein the watermark encodes a plurality of bits of data.
16. The computer implemented method of claim 15 , wherein a first bit is encoded by a first set of selected segments, and a second bit is encoded by a second set of selected segments.
17. The computer implemented method of claim 16 , wherein the first and second sets of selected segments are non-overlapping.
18. The computer implemented method of claim 16 , wherein the first and second sets of selected segments are interlaced with each other.
19. The computer implemented method of claim 16 , wherein a third bit is encoded by a third set of selected segments.
20. The computer implemented method of claim 19 , wherein the third set of segments differs from the first and second set of segments.
21. The computer implemented method of claim 20 , wherein the first, second and third sets of selected segments are non-overlapping.
22. The computer implemented method of claim 20 , wherein the first, second and third sets of segments are interlaced with each other.
23. The computer implemented method of claim 1 being performed without accessing a netlist.
24. The computer implemented method of claim 1 , wherein the watermark is based exclusively on the number of geometric structures in the selected segments.
25. The computer implemented method of claim 1 , wherein the number of geometric structures in a selected segment of a selected layer of the circuit design layout is altered to form a three-dimensional watermark.
26. A computer implemented method for watermarking a circuit design layout, comprising:
dividing a circuit design layout into a plurality of segments;
selecting one or more segments from the plurality of segments; and
generating a watermark in the circuit design layout by modifying, using a routing machine that comprises at least one processor, routing of the circuit design layout to alter the number of vias in the circuit design layout in the one or more segments that are selected.
27. The computer implemented method of claim 26 , wherein the selected segments are randomly distributed.
28. The computer implemented method of claim 26 , wherein the number of vias in the selected segments is altered by about 1-10% compared to the number of vias in unselected segments.
29. The computer implemented method of claim 26 , wherein the number of vias in the selected segments is less than the number of vias in unselected segments.
30. The computer implemented method of claim 26 , wherein the number of vias in the selected segments is greater than the number of vias in unselected segments.
31. The computer implemented method of claim 26 , wherein the watermark encodes a bit of data.
32. The computer implemented method of claim 26 , wherein the watermark encodes a plurality of bits of data.
33. The computer implemented method of claim 32 , wherein a first bit is encoded by a first set of selected segments, and a second bit is encoded by a second set of selected segments.
34. The computer implemented method of claim 33 , wherein the first and second sets of selected segments are non-overlapping.
35. The computer implemented method of claim 33 , wherein the first and second sets of selected segments are interlaced with each other.
36. The computer implemented method of claim 26 being performed without accessing a netlist.
37. The computer implemented method of claim 26 , wherein the number of vias in a selected segment of a selected layer of the circuit design layout is altered to form a three-dimensional watermark.
38. A computer implemented method for watermarking a circuit design layout, comprising the steps of:
dividing a circuit design layout into a plurality of segments;
selecting one or more segments from the plurality of segments; and
generating a watermark in the circuit design layout by modifying, by using a routing machine that comprises at least one processor, routing of the circuit design layout to alter the number of jogs in the circuit design layout in the selected segments.
39. The computer implemented method of claim 38 , wherein the selected segments are randomly distributed.
40. The computer implemented method of claim 38 , wherein the number of jogs in the selected segments is altered by about 1-10% compared to the number of jogs in unselected segments.
41. The computer implemented method of claim 38 , wherein the number of jogs in the selected segments is less than the number of jogs in unselected segments.
42. The computer implemented method of claim 38 , wherein the number of jogs in the selected segments is greater than the number of jogs in unselected segments.
43. The computer implemented method of claim 38 , wherein the watermark encodes a bit of data.
44. The computer implemented method of claim 38 , wherein the watermark encodes a plurality of bits of data.
45. The computer implemented method of claim 44 , wherein a first bit is encoded by a first set of selected segments, and a second bit is encoded by a second set of selected segments.
46. The computer implemented method of claim 45 , wherein the first and second sets of selected segments are non-overlapping.
47. The computer implemented method of claim 45 , wherein the first and second sets of selected segments are interlaced with each other.
48. The computer implemented method of claim 38 being performed without accessing a netlist.
49. A computer implemented method for watermarking a circuit design layout, comprising the steps of:
dividing a circuit design layout into a plurality of segments;
selecting one or more segments from the plurality of segments; and
generating a watermark in the circuit design layout by altering, using a routing machine that comprises at least one processor, the gap between line ends in the selected segments.