Asynchronous sample rate correction by time domain interpolation

1. A circuit configured to correct a sample rate by way of time domain interpolation, comprising:

a first circuit loop having an up/down counter configured to receive an input signal and a feedback signal and an adder configured to receive a counter output signal from the up/down counter and to output a carry output as the feedback signal to the up/down counter; and

a second circuit loop configured to transmit a sum output from the adder to a modulator and to feed back a modulator output signal from the modulator to an input of the adder.

2. A method of correcting a sample rate by

receiving an input signal operating at a first frequency;

transmitting the input signal into an up input of an up/down counter;

transmitting an output signal from the up/down counter to a first input of an adder;

transmitting output of the adder into a modulator, where the modulator is clocked at a second frequency, and wherein the modulator produces a modulator output that is fed back as a second input of the adder; and

if an overflow occurs at the adder, transmitting a carry output from the adder that is fed back to a down input of the up/down counter to reset the up/down counter.

3. The method according to claim 2 , further comprising:

adding the output signal of the up/down counter to the modulator output from the modulator using the adder.

4. A circuit configured to correct sample rates by way of time domain interpolation, comprising:

a first circuit loop having a first up/down counter configured to receive a first input signal at a first input frequency and a first feedback signal and a first adder configured to receive a first counter output signal from the first up/down counter and to output a first carry output as the first feedback signal to the first up/down counter;

a second circuit loop configured to transmit a first sum output from the first adder to a first modulator and to feed back a first modulator output signal from the first modulator to a first input of the first adder, wherein the first modulator output signal has a first output frequency greater than the first input frequency;

a third circuit loop having a second up/down counter configured to receive a second feedback signal and a second input signal at a second input frequency different from the first input frequency and a second adder configured to receive a second counter output signal from the second up/down counter and to output a second carry output as the second feedback signal to the second up/down counter; and

a fourth circuit loop configured to transmit a second sum output from the second adder to a second modulator and to feed back a second modulator output signal from the second modulator to a second input of the second adder, wherein the second modulator output signal has the first output frequency greater than the second input frequency.

5. A method of correcting a sample rate by

receiving a first input signal operating at a first input frequency;

transmitting the first input signal into a first up input of a first up/down counter;

transmitting a first output signal from the first up/down counter to a first input of a first adder;

transmitting output of the first adder into a first modulator, where the first modulator is clocked at a first output frequency greater than the first input frequency, and wherein the first modulator produces a first modulator output that is fed back as a second input of the first adder; and

if an overflow occurs at the first adder, transmitting a first carry output from the first adder that is fed back to a first down input of the first up/down counter to reset the first up/down counter;

receiving a second input signal operating at a second input frequency;

transmitting the second input signal into a second up input of a second up/down counter;

transmitting a second output signal from the second up/down counter to a first input of a second adder;

transmitting output of the second adder into a second modulator, where the second modulator is clocked at the first output frequency greater than the second input frequency, and wherein the second modulator produces a second modulator output that is fed back as a second input of the second adder; and

if an overflow occurs at the second adder, transmitting a second carry output from the second adder that is fed back to a second down input of the second up/down counter to reset the second up/down counter.

6. The method according to claim 5 , further comprising:

adding the first output signal of the first up/down counter to the first modulator output from the first modulator using the first adder.

7. The method according to claim 5 , further comprising:

adding the second output signal of the second up/down counter to the second modulator output from the second modulator using the second adder.

8. The method according to claim 5 , further comprising:

adding the first output signal of the first up/down counter to the first modulator output from the first modulator using the first adder; and

adding the second output signal of the second up/down counter to the second modulator output from the second modulator using the second adder.

9. The circuit of claim 4 , wherein the first input frequency is 44.1 kHz.

10. The circuit of claim 4 , wherein the second input frequency is 48 kHz.

11. The circuit of claim 4 , wherein the first output frequency is 27 MHz.

12. The method of claim 5 , wherein the first input frequency is 44.1 kHz.

13. The method of claim 5 , wherein the second input frequency is 48 kHz.

14. The method of claim 5 , wherein the first output frequency is 27 MHz.

15. The circuit of claim 4 , further comprising:

circuitry mixing the first modulator output signal having the first output frequency with the second modulator output signal having the first output frequency.

16. The method of claim 5 , further comprising:

mixing the first modulator output having the first output frequency with the second modulator output having the first output frequency.

17. A circuit, comprising:

a first circuit loop having a first up/down counter configured to receive a first input signal at a first input frequency and a first feedback signal and a first adder configured to receive a first counter output signal from the first up/down counter and to output a first carry output as the first feedback signal to the first up/down counter;

a second circuit loop configured to transmit a first sum output from the first adder to a first modulator and to feed back a first modulator output signal from the first modulator to a first input of the first adder, wherein the first modulator output signal has a first output frequency greater than the first input frequency;

circuitry mixing the first modulator output signal having the first output frequency with a mixer input signal having the first output frequency, wherein the mixer input signal was processed from a second input signal having a second input frequency less than the first output frequency.

18. The circuit of claim 17 , wherein the first input frequency is 44.1 kHz.

19. The circuit of claim 17 , wherein the first input frequency is 48 kHz.

20. The circuit of claim 17 , wherein the first output frequency is 27 MHz.

21. A method, comprising:

receiving a first input signal operating at a first input frequency;

transmitting the first input signal into a first up input of a first up/down counter;

transmitting a first output signal from the first up/down counter to a first input of a first adder;

transmitting output of the first adder into a first modulator, where the first modulator is clocked at a first output frequency greater than the first input frequency, and wherein the first modulator produces a first modulator output that is fed back as a second input of the first adder;

if an overflow occurs at the first adder, transmitting a first carry output from the first adder that is fed back to a first down input of the first up/down counter to reset the first up/down counter; and

mixing the first modulator output having the first output frequency with a mixer input signal having the first output frequency, wherein the mixer input signal was processed from a second input signal having a second input frequency less than the first output frequency.

22. The method according to claim 21 , further comprising:

adding the first output signal of the first up/down counter to the first modulator output from the first modulator using the first adder.

23. The method of claim 21 , wherein the first input frequency is 44.1 kHz.

24. The method of claim 21 , wherein the first input frequency is 48 kHz.

25. The method of claim 21 , wherein the first output frequency is 27 MHz.

26. The method of claim 1 , wherein the input signal is an audio signal.

27. The method of claim 2 , wherein the input signal is an audio signal.

28. The method of claim 4 , wherein the first input signal is an audio signal.

29. The method of claim 4 , wherein the second input signal is an audio signal.

30. The method of claim 5 , wherein the first input signal is an audio signal.

31. The method of claim 5 , wherein the second input signal is an audio signal.

32. The method of claim 17 , wherein the first input signal is an audio signal.

33. The method of claim 21 , wherein the first input signal is an audio signal.

34. The method of claim 21 , wherein the second input signal is an audio signal.