Liquid crystal display panel and fabricating method thereof

1. A liquid crystal display panel, comprising:

a color filter array substrate provided with a main column spacer and a sub column spacer; and

a thin film transistor array substrate disposed in opposition to the color filter array substrate,

wherein the thin film transistor array substrate comprises:

a top film in contact with the main column spacer and a depressed portion disposed under the sub column spacer;

a gate line and a data line crossing each other with a gate insulating film disposed therebetween;

a thin film transistor provided at each crossing of the gate line and the data line; and

a protective film having a contact hole for exposing a drain electrode of the thin film transistor;

wherein the depressed portion includes at least one of the protective film and the gate insulating film and at least one of the protective film and gate insulating film has a thinner thickness at an area overlapped with the sub column spacer than an area overlapped with the main column spacer.

2. The liquid crystal display panel as claimed in claim 1 , wherein the thin film transistor array substrate further comprises:

a pixel electrode connected, via the contact hole, to the drain electrode of the thin film transistor; and

a lower alignment film formed on the pixel electrode and the protective film, the lower alignment film being the top film.

3. The liquid crystal display panel as claimed in claim 2 , wherein at least one of the main column spacer and the sub column spacer overlies one of the gate line and the data line.

4. The liquid crystal display panel as claimed in claim 2 , further comprising a storage capacitor including a pixel electrode overlying the gate line with the gate insulating film and the protective film therebetween.

5. The liquid crystal display panel as claimed in claim 4 , wherein at least one of the main column spacer and the sub column spacer does not overlie the storage capacitor.

6. The liquid crystal display panel as claimed in claim 1 , wherein the sub column spacer is inserted into the depressed portion when an outside pressure is applied.

7. A method of fabricating a liquid crystal display panel comprising:

preparing a color filter array substrate provided with a main column spacer and a sub column spacer;

forming a thin film transistor array substrate in opposition to the color filter array substrate, wherein the forming of the thin film transistor array substrate comprises forming a depressed portion thereon; and

joining the thin film transistor array substrate to the color filter array substrate with the main column spacer therebetween, wherein the depressed portion is disposed below the sub column spacer,

wherein forming a depressed portion on the thin film transistor array substrate includes:

forming a gate pattern including a gate line and gate electrode on a lower substrate;

forming a gate insulating film on the gate pattern;

forming a data line crossing the gate line, and a thin film transistor connected to the data line;

forming a protective film having a contact hole for exposing a drain electrode of the thin film transistor; and

forming a pixel electrode connected, via the contact hole, to the drain electrode of the thin film transistor,

wherein at least one of forming the gate insulating film and forming the protective film comprises forming the depressed portion; and

wherein at least one of the protective film and gate insulating film has a thinner thickness at an area overlapped with the sub column spacer than an area overlapped with the main column spacer.

8. The method as claimed in claim 7 , wherein the sub column spacer is inserted into the depressed portion when an outside pressure is applied.

9. The method as claimed in claim 7 , wherein forming the depressed portion includes:

sequentially forming a gate metal layer, a gate insulating material and a photoresist;

carrying out an exposure process and development process using a slit mask having a transmitting portion, a shielding portion and a slit portion on the photoresist, including exposing a gate insulating material and forming a photoresist pattern including a portion of a relatively low height;

patterning the gate insulating material and the gate metal layer using the photoresist pattern as a mask, thereby forming a gate insulating film overlying the gate pattern;

ashing the photoresist pattern and removing the portion of a relatively low height, thereby exposing a portion of the gate insulating film; and

partially removing the exposed gate insulating film by using a portion of the photoresist pattern left by the ashing process as a mask.

10. The method as claimed in claim 7 , wherein forming the depressed portion includes:

sequentially forming an insulating material and a photoresist on a lower substrate provided with the data line and the thin film transistor array substrate;

carrying out an exposure process and development process using a slit mask having a transmitting portion, a shielding portion and a slit portion on the photoresist, including exposing the protective material and forming a photoresist pattern having a portion of a relatively low height;

patterning the gate insulating material by using the photoresist pattern as a mask, thereby forming a protective film having a contact hole for exposing the drain electrode;

ashing the photoresist pattern and removing the portion of a relatively low height, thereby exposing one portion of the protective film; and

partially removing the exposed protective film by using a portion of the photoresist pattern left by the ashing process as a mask.

11. The method as claimed in claim 7 , wherein at least one of the main column spacer and the sub column spacer is disposed at an area overlying any one of the gate line and the data line.

12. The method as claimed in claim 7 , further comprising:

forming a storage capacitor including a pixel electrode overlying the gate line with the gate insulating film and the protective film therebetween.

13. The method as claimed in claim 12 , wherein at least one of the main column spacer and the sub column spacer does not overlie the storage capacitor.