Process for fabricating an integrated circuit comprising a photodiode, and corresponding integrated circuit
An integrated circuit includes at least one photodiode associated with a transfer transistor. The photodiode is formed with an upper pn junction. The transfer transistor includes a lateral spacer located on a side facing the photodiode. An upper layer of the upper pn junction includes a lateral surface extension lying beneath the spacer. A lower layer of the upper pn junction forms a source/drain region for the transfer transistor. An edge of the lateral surface extension lying beneath the spacer and adjacent a gate of the transfer transistor contacts a substrate of the integrated circuit. An oxide layer insulating the gate from the underlying substrate does not overlie the lateral surface extension of the upper layer underneath of the lateral spacer.
1. An integrated circuit comprising:
a photodiode formed in a semiconductor substrate and including an upper pn junction comprising a buried semiconductor region having a first type of conductivity and an overlying surface layer having a second type of conductivity;
a transfer transistor associated with the photodiode comprising an insulated gate; and
lateral spacers for the insulated gate at least one of which overlies a lateral surface extension portion of the overlying surface layer having the second type of conductivity;
wherein the lateral surface extension portion has a first constant thickness extending for a first distance underneath the at least one lateral spacer;
wherein the overlying surface layer further has a second constant thickness extending for a second distance outside the lateral spacer; and
wherein the buried semiconductor region of the photodiode is also a source region for the transfer transistor, and further wherein the buried semiconductor region does not contact an insulating layer associated with the insulated gate.
2. The circuit of claim 1 wherein an inside edge of the lateral surface extension of the overlying surface layer is aligned with an edge of the insulated gate.
3. The circuit of claim 2 wherein the inside edge of the lateral surface extension of the overlying surface layer contacts the semiconductor substrate.
4. The circuit of claim 1 , wherein the first constant thickness of the lateral surface extension of the overlying surface layer is less than 20 nm.
5. The circuit of claim 1 wherein the lateral surface extension of the overlying surface layer beneath the at least one lateral spacer is thinner than the overlying surface layer outside of the at least one lateral spacer.
6. The circuit of claim 1 wherein an inside edge of the lateral surface extension of the overlying surface layer adjacent the insulated gate contacts the semiconductor substrate.
7. The circuit of claim 1 wherein a gate oxide separates the insulated gate from the semiconductor substrate and wherein the gate oxide does not overlie the lateral surface extension of the surface layer underneath of the lateral spacer, and further wherein the buried semiconductor region does not contact the gate oxide underneath the insulated gate.
8. The circuit of claim 1 wherein a thickness transition region of the overlying surface layer from the first constant thickness to the second constant thickness is aligned with an outside edge of the lateral spacer.
9. The integrated circuit according to claim 1 , wherein the first distance is substantially a width of the lateral spacer and the second distance is substantially a width of the overlying surface layer outside the lateral spacer.
10. An integrated circuit comprising:
a photodiode formed in a semiconductor substrate and including an upper pn junction comprising a buried semiconductor region having a first type of conductivity and an overlying surface layer having a second type of conductivity;
a transfer transistor associated with the photodiode comprising an insulated gate;
lateral spacers for the insulated gate at least one of which overlies a lateral surface extension portion of the overlying surface layer having the second type of conductivity;
wherein the lateral surface extension portion has a first constant thickness extending for a first distance underneath the at least one lateral spacer;
wherein the overlying surface layer further has a second constant thickness extending for a second distance outside the lateral spacer; and
wherein a gate oxide separates the insulated gate from the semiconductor substrate and wherein the gate oxide does not overlie the lateral surface extension of the surface layer underneath of the lateral spacer, and further wherein the buried semiconductor region does not contact the gate oxide underneath the insulated gate.