Thin film transistor array panel
View Patent ↗A liquid crystal display that includes a substrate; a plurality of gate lines formed on the substrate; a plurality of common electrodes formed on the substrate and made of a transparent material; a plurality of data lines intersecting the gate lines; a plurality of thin film transistors connected to the data lines and the gate lines; and a plurality of pixel electrodes connected to the thin film transistors and overlapping the common electrodes. The pixel electrodes include a first sub-pixel electrode separated by a distance from a second sub-pixel electrode.
1. A thin film transistor array panel comprising:
a substrate;
a plurality of gate lines formed on the substrate;
a plurality of common electrodes formed on the substrate and made of transparent material;
a plurality of data lines intersecting the gate lines;
a plurality of thin film transistors connected to the data lines and the gate lines; and
a plurality of pixel electrodes connected to the thin film transistors and overlapping the common electrodes,
wherein the pixel electrodes include a first sub-pixel electrode separated a distance from a second sub-pixel electrode.
2. The thin film transistor array panel of claim 1 , wherein the thin film transistors comprise a first drain electrode connected to the first pixel electrode and a second drain electrode connected to the second pixel electrode.
3. The thin film transistor array panel of claim 1 , wherein the first and second sub-pixel electrodes comprise a plurality of branch electrodes having a parallel arrangement.
4. The thin film transistor array panel of claim 3 , wherein the common electrodes have a continuous surface between the branch electrodes.
5. The thin film transistor array panel of claim 3 , wherein the branch electrodes of the first and second sub-pixel electrodes are disposed in different areas.
6. The thin film transistor array panel of claim 5 , wherein the first and second sub-pixel electrodes are disposed on both sides of the gate lines.
7. The thin film transistor array panel of claim 3 , wherein the branch electrodes of the first sub-pixel electrode are alternatively arranged with the branch electrodes of the second sub-pixel electrode.
8. The thin film transistor array panel of claim 3 , wherein the branch electrodes of the first and second sub-pixel electrodes are curved with respect to the gate lines or the data lines.
9. The thin film transistor array panel of claim 8 , wherein the branch electrodes of the first and second sub-pixel electrodes have inversion symmetry with respect to center lines of the common electrodes and are parallel to the gate lines.
10. The thin film transistor array panel of claim 3 , further comprising a plurality of common electrode lines connecting the common electrodes.