Variable transconductance circuit

1. A variable transconductance circuit comprising:

a voltage-current conversion circuit for outputting a current signal linear with an input voltage signal;

first and second MOS transistors for converting the current signal received to a square-root compressed or approximately square-root compressed voltage signal; and

third and fourth MOS transistors for converting the square-root compressed or approximately square-root compressed voltage signal to a linear current signal, wherein:

transconductance is controlled by varying a bias current for the first and second MOS transistors and a bias current for the third and fourth MOS transistors,

the voltage-current conversion circuit comprises:

two operational amplifiers into which the input voltage signal is input; and

a resistance interposed between outputs of the two operational amplifiers,

each of the outputs of the two operational amplifiers serves as a source follower biased with a first current source or a second current source, and the current signal is taken from a drain of the source follower,

gates of the first and second MOS transistors are biased with a predetermined bias voltage, and the current signal output from the voltage-current conversion circuit is input into sources of the first and second MOS transistors,

sources of the third and fourth MOS transistors are common-connected, a third current source is connected to the common-connected sources, and a gate of the third MOS transistor is connected to a source of one of the first and second MOS transistors while a gate of the fourth MOS transistor is connected to a source of the other first or second MOS transistor,

the variable transconductance circuit uses drains of the third and fourth MOS transistors as current outputs, and controls transconductance by varying the current from the first and second current sources and the current from the third current source.

2. A variable transconductance circuit comprising:

a voltage-current conversion circuit for outputting a current signal linear with an input voltage signal;

first and second MOS transistors for converting the current signal received to a square-root compressed or approximately square-root compressed voltage signal; and

third and fourth MOS transistors for converting the square-root compressed or approximately square-root compressed voltage signal to a linear current signal, wherein:

transconductance is controlled by varying a bias current for the first and second MOS transistors and a bias current for the third and fourth MOS transistors,

each of the first and second MOS transistors or the third and fourth MOS transistors is composed of a plurality of MOS transistors connected in parallel, and transconductance is controlled by switching.

3. A variable transconductance circuit comprising:

a voltage-current conversion circuit for outputting a current signal linear with an input voltage signal;

first and second MOS transistors for converting the current signal received to a square-root compressed or approximately square-root compressed voltage signal; and

third and fourth MOS transistors for converting the square-root compressed or approximately square-root compressed voltage signal to a linear current signal, wherein:

transconductance is controlled by varying a bias current for the first and second MOS transistors and a bias current for the third and fourth MOS transistors,

the variable transconductance circuit further comprises a transconductance control circuit for generating the bias currents,

the transconductance control circuit comprises:

a square circuit comprising a trans-linear loop circuit including vertically-connected seventh and eighth MOS transistors with a gate and drain of each transistor being connected to each other, a ninth MOS transistor of which gate is connected to the gate of the eighth MOS transistor, and a tenth MOS transistor of which gate is connected to a source of the ninth MOS transistor, the square circuit comprising a supply means for increasing a current flowing through each of the ninth and tenth MOS transistors by several times and supplying the resultant current to the seventh and eighth MOS transistors, the square circuit using a drain of the eighth MOS transistor as a current input, and connecting one of the ninth and tenth MOS transistors to a fourth current source while outputting a current flowing through the other ninth or tenth MOS transistor as a current mirror output, and

the current mirror output serves as the bias current.

4. The variable transconductance circuit of claim 3 , wherein the supply means includes a current mirror for increasing a current flowing through each of the ninth and tenth MOS transistors by several times and supplying the resultant current to the seventh and eighth MOS transistors.

5. The variable transconductance circuit of claim 3 , wherein the mirror ratio of the current mirror output is variable.

6. The variable transconductance circuit of claim 3 , wherein the current value of the fourth current source is variable.