Single gate oxide level shifter

1. A level shifter for interfacing a first circuit operating at a first voltage higher than a ground voltage with a second circuit operating at a second voltage higher than the first voltage, comprising:

a first inverter coupled between the second voltage and the first voltage;

a second inverter coupled between the second voltage and the first voltage, the second inverter being cross-coupled with the first inverter for latching a value therein;

a first switch module comprising a PMOS transistor having a source coupled to the first inverter and a gate coupled to the first voltage via a first resistor to reduce a voltage difference between the gate and the source of the PMOS transistor, and an NMOS transistor having a source coupled to an input signal and a drain coupled to the PMOS transistor; and

a second switch module coupled between a data storage node of the first and second inverters and an inverted input signal swinging between the ground voltage and the first voltage,

wherein the first and second inverters and the first and second switch modules include one or more MOS transistors with gate oxide layers of the same thickness.

2. The level shifter of claim 1 wherein the first inverter comprises a first PMOS transistor having its source coupled to the second voltage, and a first NMOS transistor having its drain coupled to a drain of the first PMOS transistor, the first PMOS and NMOS transistors having gates connected together.

3. The level shifter of claim 2 wherein the second inverter comprises a second PMOS transistor having its source coupled to the second voltage, and a second NMOS transistor having its drain coupled to a drain of the second PMOS transistor, the second PMOS and NMOS transistors having gates connected together.

4. The level shifter of claim 3 wherein the gates of the first PMOS and NMOS transistors are coupled to the drains of the second PMOS and NMOS transistors, and the gates of the second PMOS and NMOS transistors are coupled to the drains of the first PMOS and NMOS transistors.

5. The level shifter of claim 1 wherein the second switch module comprises a third PMOS transistor having a source coupled to the drains of the second PMOS and NMOS transistors, and a third NMOS transistor having a drain coupled to a drain of the third PMOS transistor and a source coupled to the inverted input signal.

6. The level shifter of claim 5 further comprising an inverter coupled between the sources of the NMOS transistor and third NMOS transistor.

7. The level shifter of claim 5 wherein the gate of the third PMOS transistor is coupled to the first voltage via the first resistor.

8. The level shifter of claim 6 wherein the gates of the NMOS transistor and third NMOS transistor are coupled to the first voltage via a second resistor.

9. The level shifter of claim 1 wherein the gate oxide layer has a thickness no greater than 40 angstroms.

10. A level shifter for interfacing a first circuit operating at a first voltage higher than a ground voltage with a second circuit operating at a second voltage higher than the first voltage, comprising:

a first PMOS transistor having its source coupled to the second voltage;

a first NMOS transistor coupled between the first PMOS transistor and the first voltage, the first PMOS and NMOS transistors having gates connected together;

a second PMOS transistor having its source coupled to the second voltage;

a second NMOS transistor coupled between the second PMOS transistor and the first voltage, the second PMOS and NMOS transistors having gates connected to the drains of the first PMOS and NMOS transistors, the first PMOS and NMOS transistors having gates connected to the drains of the second PMOS and NMOS transistors;

a first switch module comprising a third PMOS transistor having a source coupled to a drain of the first PMOS transistor, a gate coupled to the first voltage via a first resistor to reduce a voltage difference between the gate and the source of the third PMOS transistor and a third NMOS transistor having a source coupled to an input signal and a drain coupled to the third PMOS transistor; and

a second switch module coupled between the drain of second PMOS transistor and an inverted input signal swinging between the ground voltage and the first voltage.

11. The level shifter of claim 10 wherein the second switch module comprises a fourth PMOS transistor having a source coupled to the drains of the second PMOS and NMOS transistors, and a fourth NMOS transistor having a drain coupled to a drain of the fourth PMOS transistor and a source coupled to the inverted input signal.

12. The level shifter of claim 11 further comprising an inverter coupled between the sources of the third and fourth NMOS transistors.

13. The level shifter of claim 12 wherein the gate of the fourth PMOS transistor is coupled to the first voltage via the first resistor.

14. The level shifter of claim 10 wherein the gates of the third and fourth NMOS transistors are coupled to the first voltage via a second resistor.

15. A level shifter for interfacing a first circuit operating at a first voltage higher than a ground voltage with a second circuit operating at a second voltage higher than the first voltage, comprising:

a first PMOS transistor having its source coupled to the second voltage;

a first NMOS transistor coupled between the first PMOS transistor and the first voltage, the first PMOS and NMOS transistors having gates connected together;

a second PMOS transistor having its source coupled to the second voltage;

a second NMOS transistor coupled between the second PMOS transistor and the first voltage, the second PMOS and NMOS transistors having gates connected to the drains of the first PMOS and NMOS transistors, the first PMOS and NMOS transistors having gates connected to the drains of the second PMOS and NMOS transistors;

a third PMOS transistor having a source coupled to the drains of the first PMOS and NMOS transistors, and a gate coupled to the first voltage via a first resistor to reduce a voltage difference between the gate and the source of the third PMOS transistor;

a third NMOS transistor having a drain coupled to a drain of the third PMOS transistor and a source coupled to an input signal;

a fourth PMOS transistor having a source coupled to the drains of the second PMOS and NMOS transistors; and

a fourth NMOS transistor having a drain coupled to a drain of the fourth PMOS transistor and a source coupled to an inverted input signal,

wherein the first, second, third and fourth PMOS and NMOS transistors have gate oxide layers of the same thickness.

16. The level shifter of claim 15 further comprising an inverter coupled between the sources of the third and fourth NMOS transistors.

17. The level shifter of claim 15 wherein the gate of the fourth PMOS transistor is coupled to the first voltage via the first resistor.

18. The level shifter of claim 15 wherein the gates of the third and fourth NMOS transistors are coupled to the first voltage via a second resistor.