Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding
View Patent ↗One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.
1. A defect-and-failure tolerant demultiplexer comprising:
a number of address lines that receive input addresses;
a number of output signal lines, each corresponding to an address;
a number of signal lines complementary to the number of address lines; and
a number defect-tolerant reversibly switchable interconnections that interconnect address lines and complementary signal lines to the output signal lines so that the output signal line corresponding to an input address is selected by the demultiplexer.
2. The defect-and-failure tolerant demultiplexer of claim 1 wherein the defect-tolerant reversibly switchable interconnections include serially redundant transistors in each of a number of parallel, redundant branches.
3. The defect-and-failure tolerant demultiplexer of claim 2 wherein the defect-tolerant reversibly switchable interconnections are 2S×2P compound transistors.
4. The defect-and-failure tolerant demultiplexer of claim 2 wherein the defect-tolerant reversibly switchable interconnections are higher-order nS×mP transistors that are both short-defective-component-transistor tolerant and open-defective-component-transistor tolerant.
5. The defect-and-failure tolerant demultiplexer of claim 1 wherein the defect-tolerant reversibly switchable interconnections include a number n of serially redundant transistors in each of a number m branches, wherein n is greater than m, wherein n is greater than or equal to 2, and wherein m is greater than or equal to 1.
6. The defect-and-failure tolerant demultiplexer of claim 5 further including:
supplemental signal lines and supplemental complementary signal lines and additional reversibly switchable interconnections;
an encoder circuit that generates an internal, coded address from an input address;
reversibly switchable interconnections that interconnect the supplemental signal lines and supplemental complementary signal lines to the output signal lines so that the output signal line corresponding to an internal, coded address is selected by the demultiplexer.
7. The defect-and-failure tolerant demultiplexer of claim 6 wherein the encoder circuit generates an internal, coded address from an input address according to an [n′, k, d] linear block code and wherein the defect-and-failure tolerant demultiplexer tolerates d−1 open-defective reversibly switchable interconnections connected to each output signal line and tolerates shorts in one less than the number of serially linked transistors in each reversibly switchable interconnection.
8. A method for fabricating a defect-and-failure tolerant demultiplexer, the method comprising:
selecting an address size k;
selecting a number of output signal lines m′ equal to or less than 2 k ; and
fabricating the defect-and-failure tolerant demultiplexer to include
k address lines that receive input addresses;
m′ output signal lines, each corresponding to a k-bit address;
k signal lines complementary to the number of address lines; and
a number defect-tolerant reversibly switchable interconnections that interconnect address lines and complementary signal lines to the output signal lines so that the output signal line corresponding to an input address is selected by the demultiplexer.
9. The method of claim 8 further including fabricating defect-tolerant reversibly switchable interconnections that include serially redundant transistors in each of a number of parallel, redundant branches.
10. The method of claim 9 further including fabricating compound transistors as defect-tolerant reversibly switchable interconnections.
11. The method of claim 9 further including fabricating higher-order multi-transistor reversibly switchable interconnections that are both short-defective-component-transistor tolerant and open-defective-component-transistor tolerant as defect-tolerant reversibly switchable interconnections.
12. The method of claim 8 further including fabricating defect-tolerant reversibly switchable interconnections that each includes a number n of serially redundant transistors in each of a number m branches, wherein n is greater than m, wherein n is greater than or equal to 2, and wherein m is greater than or equal to 1.
13. The method of claim 12 further including:
fabricating supplemental signal lines and supplemental complementary signal lines;
fabricating an encoder circuit that generates an internal, coded address from an input address; and
fabricating additional reversibly switchable interconnections that interconnect the supplemental signal lines and supplemental complementary signal lines to the output signal lines so that the output signal line corresponding to an internal, coded address is selected by the demultiplexer.
14. The method of claim 13 wherein the encoder circuit generates an internal, coded address from an input address according to an [n′, k, d] linear block code and wherein the defect-and-failure tolerant demultiplexer tolerates d−1 open-defective reversibly switchable interconnections connected to each output signal line and tolerates n−1 short-defective transistors in each reversibly switchable interconnection.