IP Library Granted Patent US 7,504,874
Granted Patent B2
US 7,504,874 · App. 11/485,576 · Granted Mar 17, 2009

Transistor arrangement with temperature compensation and method for temperature compensation

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Quick Facts
Patent No.
US 7,504,874
App. No.
11/485,576
Granted
Mar 17, 2009
Kind
B2
Abstract

A transistor arrangement with temperature compensation is disclosed with a transistor having at least one adjustable geometric parameter. A temperature measuring means outputs a temperature-dependent signal, depending on which a control unit drives the geometric parameter of the transistor in such a way that the electrical characteristic quantities thereof are temperature-independent. The adjustable geometric parameter may be the channel width of the transistor.

Claims (19)

1. A transistor arrangement with temperature compensation, comprising:

at least one transistor comprising a control input, a controlled path, and at least one adjustable geometric parameter;

a temperature measuring means configured to output a temperature-dependent signal;

a control unit configured to set the at least one geometric parameter of the transistor based on the temperature-dependent signal; and

a comparator coupled to the control unit, and comprising inputs configured to receive a temperature-independent signal and the temperature-dependent signal,

wherein the at least one transistor comprises a plurality of partial transistors each connected in a series circuit with an assigned switching transistor, wherein the series circuits each comprise a partial transistor and a switching transistor, and wherein each of the series circuits are connected together in parallel with one another, and wherein the switching transistors each have a control input coupled to the control unit.

2. The transistor arrangement of claim 1 , wherein the transistor comprises a unipolar transistor, and the at least one geometric parameter comprises a channel length or a channel width of the transistor.

3. The transistor arrangement of claim 1 , further comprising a bandgap circuit configured to generate the temperature-independent signal, wherein the bandgap circuit is connected indirectly or directly to a first input of the comparator.

4. The transistor arrangement of claim 1 , further comprising a control loop comprising a further transistor having at least one adjustable geometric parameter, the further transistor coupled to the control unit and controlled thereby, and coupled to a second input of the comparator, there being connected to a first input of the comparator a means for feeding in the temperature-independent signal that is composed of a partial value of a bandgap voltage and the threshold voltage of a transistor that serves as a reference variable for the control loop.

5. The transistor arrangement of claim 1 , further comprising an assignment table coupled between the temperature sensor and the control unit, and configured to assign a correction value to the temperature-dependent signal.

6. The transistor arrangement of claim 1 , wherein the temperature measuring means comprises a transistor.

7. The transistor arrangement of claim 1 , wherein the partial transistors each comprise metal insulator semiconductor transistors.

8. The transistor arrangement of claim 7 , wherein each assigned switching transistor is connected to a drain terminal of its respective partial transistor.

9. A method for temperature compensation of a transistor, comprising:

measuring a temperature and providing a temperature-dependent signal based thereon; and

controlling at least one adjustable geometric parameter of at least one transistor based on the temperature-dependent signal, wherein controlling the geometric parameter comprises varying a channel length of the transistor based on the temperature-dependent signal.

10. The method of claim 9 , wherein controlling the geometric parameter further comprises varying a channel width of the transistor based on the temperature-dependent signal.

11. The method of claim 10 , wherein the channel width of the transistor is varied by respectively switching in and out a plurality of partial transistors selectively connected together in parallel.

12. The method of claim 9 , wherein the channel length is varied by respectively switching in and out a plurality of partial transistors selectively connected together in series.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2012
From: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 027556/0709 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2012
From: INFINEON TECHNOLOGIES AG
To: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH
Reel/Frame 027548/0623 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2006
From: OEHM, JURGEN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 018384/0808 →