Low noise phase locked loop with a high precision lock detector

1. A phase lock loop (PLL) comprising

a voltage controlled oscillator (VCO) for providing a VCO output signal, based on first and second voltage tuning signals inputted to the VCO,

a filter network for outputting the first and second voltage tuning signals to the VCO,

a first phase/frequency detector (PFD) for inputting a first signal to the filter network for forming the first and second voltage tuning signals,

a second phase/frequency detector (PFD) for inputting a second signal to the filter network for forming the first and second voltage tuning signals,

wherein the first and second voltage tuning signals provide, respectively, first and second gains of frequency per volt for controlling a frequency of the VCO output signal, and

when the first PFD is active, the filter network (a) receives the first signal from the first PFD, and responsively outputs the first voltage tuning signal to the VCO and (b) outputs a DC voltage as the second voltage tuning signal to the VCO, and

when the second PFD is active, the filter network (a) receives the second signal from the second PFD, and responsively outputs the second voltage tuning signal to the VCO and (b) outputs another DC voltage as the first voltage tuning signal to the VCO.

2. The PLL of claim 1 wherein the first voltage tuning signal has a higher gain than the second voltage tuning signal, and

the first voltage tuning signal provides coarse frequency control of the VCO output signal and the second voltage tuning signal provides fine frequency control of the VCO output signal.

3. The PLL of claim 1 wherein

the first gain of the first voltage tuning signal is greater than 1 GHz per volt and the second gain of the second voltage tuning signal is less than 500 MHz per volt.

4. The PLL of claim 1 wherein

the filter network includes resistive and capacitive elements for damping or reducing overshoot of the second voltage tuning signal.

5. The PLL of claim 1 including

a first charge pump coupled between the first PFD and the filter network for providing the first voltage tuning signal,

a second charge pump coupled between the second PFD and the filter network for providing the second voltage tuning signal, and

an enable/disable signal for enabling one of the first and second charge pumps or disabling the other one of the first and second charge pumps.

6. The PLL of claim 1 including

a frequency divider coupled to the VCO output signal,

wherein the frequency divider provides a first feedback signal to the first PFD for comparison with a first reference signal, and

a second feedback signal is provided from the VCO output signal to the second PFD for comparison with a second reference signal.

7. The PLL of claim 6 wherein

the first reference signal has a lower frequency than the second reference signal, and

the second reference signal is substantially equal to a desired frequency of the VCO output signal.

8. The PLL of claim 1 including

a frequency offset analyzer coupled to the first PFD for determining frequency lock status of the VCO output signal.

9. The PLL of claim 8 wherein

the frequency offset analyzer includes a counter for determining a period of time, T, based on the following relationship:

T =1/(reference frequency−VCO feedback frequency)

where the reference frequency is the frequency of a first reference signal, and the VCO feedback frequency is the frequency of the VCO output signal; and

when T exceeds a predetermined threshold value, the frequency lock status is determined to be correctly locked.

10. The PLL of claim 1 wherein

the DC voltages provided as the first and second voltage tuning signals to the VCO each includes an average voltage.

11. The PLL of claim 1 wherein the first and second voltage tuning signals are correlated to each other.

12. The PLL of claim 1 wherein

the filter network includes a first resistor in series with a first capacitor, one end of the first resistor connected to a first terminal providing the first voltage tuning signal, and

a second resistor in series with the first capacitor, one end of the second resistor connected to a second terminal providing the second voltage tuning signal,

when the first PFD is active, the first resistor in series with the first capacitor is configured as an integrator for providing the DC voltage as the second voltage tuning signal to the VCO, and

when the second PFD is active, the second resistor in series with the first capacitor is configured as an integrator for providing the other DC voltage as the first voltage tuning signal to the VCO.

13. A phase lock loop (PLL) comprising

a voltage controlled oscillator (VCO) for providing a VCO output signal,

a phase/frequency detector (PFD) for receiving (a) the VCO output signal and (b) a reference signal, and outputting up/down pulses,

a gate for logically combining the up/down pulses and outputting an XOR or XNOR signal,

an integrator coupled to the gate for outputting an integrated XOR or XNOR signal, and

a comparator for comparing the integrated XOR or XNOR signal to a predetermined threshold level and providing a comparator output signal having a time period dependent upon the integrated XOR or XNOR signal,

wherein when the time period of the comparator output signal exceeds a predetermined threshold time period, the VCO is providing a desired frequency for the VCO output signal.

14. The PLL of claim 13 including

an edge detector coupled to the comparator for detecting rising edges of the comparator output signal, and

a counter coupled to the edge detector for counting a time period between detected rising edges to determine the time period of the comparator output signal.

15. The PLL of claim 14 wherein

the counter determines the time period, T, based on the following relationship:

T =1/(reference frequency−VCO feedback frequency)

where the reference frequency is the frequency of the reference signal, and the VCO feedback frequency is the frequency of the VCO output signal; and

when T exceeds the predetermined threshold time period, the VCO is providing the desired frequency for the VCO output signal.

16. The PLL of claim 13 including

a charge pump coupled between the PFD and the VCO for providing a first voltage tuning signal to control the frequency of the VCO output signal.

17. The PLL of claim 16 including

another charge pump coupled between another PFD and the VCO for providing a second voltage tuning signal to control the frequency of the VCO output signal,

wherein the second voltage tuning signal has a gain of frequency per volt that is lower than a gain of frequency per volt of the first voltage tuning signal.

18. A method of controlling a frequency of a voltage controlled oscillator (VCO) having an acquisition mode and a tracking mode, the method comprising the steps of:

(a) tuning the frequency of the VCO, by way of a filter network, using a first phase/frequency detector (PFD);

(b) tuning the frequency of the VCO, by way of the filter network, using a second phase/frequency detector (PFD);

(c) enabling the first PFD and disabling the second PFD during the acquisition mode; and

(d) enabling the second PFD and disabling the first PFD during the tracking mode,

wherein when the first PFD is enabled, the filter network (a) receives a first signal from the first PFD, and responsively outputs a first voltage tuning signal to the VCO and (b) outputs a DC voltage as a second voltage tuning signal to the VCO, and

when the second PFD is enabled, the filter network (a) receives a second signal from the second PFD, and responsively outputs the second voltage tuning signal to the VCO and (b) outputs another DC voltage as the first voltage tuning signal to the VCO.

19. The method of claim 18 wherein

step (a) includes tuning the frequency of the VCO based on (i) a feedback signal f 2 derived from the VCO and (ii) a first reference signal f 1 ; and

step (b) includes tuning the frequency of the VCO based on (i) a feedback signal f 4 derived from the VCO and (ii) a second reference signal f 5 ;

wherein f 1 is approximately equal to f 2 and f 4 is approximately equal to f 5 .

20. The method of claim 19 wherein f 1 is substantially lower in frequency than f 5 .

21. The method of claim 19 wherein

a VCO output signal has an output frequency of f 4 .

22. The method of claim 19 including the steps of:

(e) generating a difference signal based on signals ft and f 2 ;

(f) comparing the difference signal to a threshold value and outputting a signal f 3 based on the comparison;

(g) measuring a period T of the outputted signal f 3 ; and

(h) determining status of the VCO based on the period T measured in step (g).