Flat panel display and method for fabricating the same
View Patent ↗A method for fabricating a flat panel display, comprising preparing an insulating substrate; forming separated source and drain electrodes on the insulating substrate to define a channel region; forming a first passivation layer on the source and drain electrodes; forming a metal layer having an opening corresponding to the channel region on the first passivation layer; forming a deposition opening in the passivation layer by using the metal layer as a mask to expose the channel region; forming an organic semiconductor layer and a second passivation layer, in turn, in the deposition opening and on the metal layer; and removing the metal layer, the organic semiconductor layer and the second passivation layer while allowing the layers formed in the deposition opening to remain.
1. A method for fabricating a flat panel display, comprising the steps of:
preparing an insulating substrate;
forming a separated source electrode and drain electrode on the insulating substrate to define a channel region;
forming a first passivation layer on the source and drain electrodes;
forming a metal layer having an opening corresponding to the channel region on the first passivation layer;
forming a deposition opening in the first passivation layer by using the metal layer as a mask to expose the channel region;
forming an organic semiconductor layer and a second passivation layer, in turn, in the deposition opening and on the metal layer; and
removing the metal layer and a portion of the organic semiconductor layer, thereby allowing the organic semiconductor layer formed in the deposition opening to remain.
2. The method as set forth in claim 1 , wherein the step of removing the metal layer is performed by a lift-off process.
3. The method as set forth in claim 2 , wherein the lift-off process uses an etchant which does not substantially affect the second passivation layer.
4. The method as set forth in claim 1 , wherein the metal layer and an upper layer on the metal layer are removed at the same time.
5. The method as set forth in claim 1 , wherein the deposition opening is formed by a wet etching process.
6. The method as set forth in claim 1 , wherein the deposition opening has a greater width than the opening.
7. The method as set forth in claim 1 , wherein at least a part of the metal layer is further extended in a direction to the deposition opening in comparison with the first passivation layer.
8. The method as set forth in claim 1 , further comprising a step of forming a data line on the insulating substrate before forming the source and drain electrodes.
9. The method as set forth in claim 8 , further comprising a step of forming an interlayer insulating film having a first contact opening, for exposing at least a part of the data line.
10. The method as set forth in claim 9 , further comprising a step of forming a gate electrode corresponding to the interlayer insulating film on the channel region.
11. The method as set forth in claim 10 , further comprising a step of forming a gate insulating film between the gate electrode and the source and drain electrodes.
12. The method as set forth in claim 1 , wherein the organic semiconductor layer is formed by an evaporation method.