Flat panel display and method for fabricating the same
View Patent ↗The invention provides a flat panel display having an insulating substrate; a data line formed on the insulating substrate; an interlayer insulating film formed on the data line having a first contact opening exposing the data line; a connecting member formed in a part of the first contact opening; an interlayer insulating film around the first contact opening; a gate insulating film formed on the connecting member having a second contact opening exposing the connecting member; and an organic semiconductor layer formed on the gate insulating film.
1. A flat panel display comprising:
an insulating substrate;
a data line formed on the insulating substrate;
an interlayer insulating film formed on the data line having a first contact opening exposing the data line;
a connecting member formed in a part of the first contact opening;
a gate insulating film formed on the connecting member having a second contact opening exposing the connecting member; and
an organic semiconductor layer formed on the gate insulating film,
wherein the second contact opening does not overlap the first contact opening.
2. The flat panel display according to claim 1 , wherein the data line comprises a data line and a data pad.
3. The flat panel display according to claim 2 , further comprising a transparent electrode layer formed on the gate insulating film, wherein the transparent electrode layer comprises a source electrode connected with the connecting member through the second contact opening and contacted to at least a part of the organic semiconductor layer, a drain electrode separated from the source electrode by the organic semiconductor layer, and a pixel electrode connected to the drain electrode.
4. The flat panel display according to claim 3 , wherein the transparent electrode layer further comprises a data pad contact member connected to the data pad.
5. The flat panel display according to claim 1 , wherein the gate insulating film is composed of organic material.
6. The flat panel display according to claim 1 , wherein a height of the connecting member exposed by the second contact opening is greater than that of the connecting member formed on the first contact opening.
7. The flat panel display according to claim 1 , further comprising a gate electrode formed on the same layer with the connecting member, wherein the gate electrode is located in a lower part of the organic semiconductor layer.
8. The flat panel display according to claim 3 , further comprising a gate line formed to intersect with the data line to define a pixel area, and a gate pad which is provided in the end of the gate line, wherein the gate line and the gate pad are formed on the same layer with the connecting member.
9. The flat panel display according to claim 8 , wherein a third contact opening to expose the gate pad is formed on the gate insulating film provided on the gate pad.
10. The flat panel display according to claim 9 , wherein the transparent electrode layer further comprises a gate pad contact part connected to the gate pad through the third contact opening.
11. The flat panel display according to claim 3 , wherein the transparent electrode layer is composed of one of ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide).
12. The flat panel display according to claim 1 , further comprising a passivation layer formed on the organic semiconductor layer.
13. The flat panel display according to claim 9 , wherein a thickness of the gate insulating film on which the second contact opening is formed is substantially the same as the thickness of the gate insulating film on which the third contact opening is formed.