Discrete filter having a tap selection circuit

1. A digital signal processing circuit comprising:

a processing chain having a selectable number of taps and progressively accumulating a sum along the taps, the processing chain comprising a serial chain of processing units and each of the processing units having a different gain; and

a tap selection circuit coupled to the processing chain to selectively establish the number of taps of the chain, the tap selection circuit comprising a multiplexer to select one of the taps as the beginning tap in the chain and set an accumulated sum at the selected tap to zero.

2. The processing circuit of claim 1 , wherein the tap selection circuit comprises:

a register storing bits indicative of the number of taps.

3. The processing circuit of claim 1 , wherein the processing circuit comprises a finite impulse response filter.

4. The processing circuit of claim 1 , wherein the processing circuit comprises an infinite impulse response filter.

5. A method comprising:

providing a processing chain line having a fixed number of taps;

disabling some of the taps of the chain comprising selecting one of the taps as the beginning tap in the delay line and setting an accumulated sum at the selected tap to zero; and

using the remaining taps to establish a finite impulse response filter.

6. The method of claim 5 , further comprising:

storing bits indicative of the number of remaining taps.

7. The method of claim 5 , further comprising:

storing rewritable indications of filter coefficients associated with the taps.

8. A system comprising:

a filter comprising:

a processing chain having a selectable number of taps and progressively accumulating a sum along the taps the processing chain comprising a serial chain of processing units and each of the processing units having a different gain;

a tap selection circuit coupled to the processing chain to selectively establish the number of taps of the chain, the tap selection circuit comprising a multiplexer to select one of the taps as the beginning tap in the chain and set an accumulated sum at the selected tap to zero; and

a processor coupled to the filter.

9. The system of claim 8 , wherein the multiplexer sets a delay at the selected tap to zero.

10. The system of claim 8 , wherein the tap selection circuit comprises:

a register storing bits indicative of the number of taps.

11. The system of claim 8 , wherein the tapped delay line comprises:

registers storing indications of filter coefficients associated with the taps.

12. The system of claim 8 , wherein the processing circuit comprises a finite impulse response filter.

13. The system of claim 8 , wherein the processing circuit comprises an infinite impulse response filter.

14. The system of claim 8 , wherein the filter filters out noise.

15. The system of claim 8 , wherein the filter reduces inter-symbol interference.

16. The system of claim 8 , wherein the filter reduces aliasing effects.

17. The system of claim 8 , wherein the processor comprises a digital signal processor.