Method of updating IC cache
View Patent ↗A method of updating a cache in an integrated circuit is provided. The integrated circuit has the cache, a memory, a processor connected to the cache, and a memory interface connected to the cache, memory and processor. In the method, (a) following a cache miss, first data associated with the cache miss from a first address is requested using the processor, (b) in response to the request, the first data and second data from the memory is fetched using the memory interface, where the second data is stored in the memory adjacent the first data, (c) the cache is updated with the first and second data via the memory interface, and (d) the cache is updated to mark the updated first and second data as valid.
1. A method of updating a cache in an integrated circuit, the integrated circuit incorporating the cache, a memory, a processor connected to the cache, and a memory interface connected to the cache, memory and processor, the method comprising the steps of:
(a) following a cache miss, requesting, using the processor, first data associated with the cache miss from a first address;
(b) in response to the request, fetching, using the memory interface, the first data and second data from the memory, the second data being stored in the memory adjacent the first data;
(c) updating the cache with the first and second data via the memory interface; and
(d) updating the cache to mark the updated first and second data as valid,
wherein the cache includes instruction and data cache, the method including performing arbitration between instruction cache misses and data cache misses such that steps (a)-(d) are performed for data cache misses before instruction cache misses.
2. A method according to claim 1 , wherein the processor is configured to attempt a cache update with the first data upon receiving the first data from the memory interface, the method further comprising the step of preventing the attempted cache update by the processor from being successful, thereby preventing interference with the cache update of steps (c) and/or (d).
3. A method according to claim 2 , wherein steps (c) and (d) are performed simultaneously.
4. A method according to claim 2 , wherein steps (c) and (d) are performed in response to the processor attempting to update the cache following step (b).
5. A method according to claim 4 , wherein the memory interface is configured to monitor the processor to determine when it attempts to update the cache following step (b).
6. A method according to claim 1 , wherein steps (c) and (d) are performed by the memory interface.