Thin film transistor substrate for display unit

1. A thin film transistor (TFT) substrate comprising:

a plastic insulation substrate;

a first barrier coating layer formed on one surface of the plastic insulation substrate;

a first hard coating layer formed on the first barrier coating layer;

a first silicon nitride layer with a first refractive index, formed on the first hard coating layer;

a TFT comprising a second silicon nitride layer with a second refractive index, wherein the second silicon nitride layer is formed on the first silicon nitride layer;

a second barrier coating layer formed on the other surface of the plastic insulation substrate;

a second hard coating layer formed on the second barrier coating layer, and

wherein the second refractive index is larger than the first refractive index.

2. The TFT substrate according to claim 1 , wherein the first silicon nitride layer has positive intrinsic stress value and the second silicon nitride layer has a negative intrinsic stress value.

3. The TFT substrate according to claim 2 , wherein the first refractive index is 1.9 or less.

4. The TFT substrate according to claim 3 , wherein a ratio of nitrogen source/silicon source in the formation of the first silicon nitride layer is larger than that in the formation of the second silicon nitride layer.

5. The TFT substrate according to claim 4 , wherein a thickness of the first silicon nitride layer is 100nm to 800nm.

6. The TFT substrate according to claim 3 , wherein a thickness of the first silicon nitride layer is 100nm to 800nm.

7. The TFT substrate according to claim 2 , wherein a ratio of nitrogen source/silicon source in the formation of the first silicon nitride layer is larger than that in the formation of the second silicon nitride layer.

8. The TFT substrate according to claim 7 , wherein a thickness of the first silicon nitride layer is 100nm to 800nm.

9. The TFT substrate according to claim 2 , wherein a thickness of the first silicon nitride layer is 100nm to 800nm.

10. The TFT substrate according to claim 1 , wherein the first refractive index is 1.9 or less.

11. The TFT substrate according to claim 10 , wherein a ratio of nitrogen source/silicon source in the formation of the first silicon nitride layer is larger than that in the formation of the second silicon nitride layer.

12. The TFT substrate according to claim 11 , wherein a thickness of the first silicon nitride layer is 100nm to 800nm.

13. The TFT substrate according to claim 10 , wherein a thickness of the first silicon nitride layer is 100nm to 800nm.

14. The TFT substrate according to claim 1 , wherein a ratio of nitrogen source/silicon source in the formation of the first silicon nitride layer is larger than that in the formation of the second silicon nitride layer.

15. The TFT substrate according to claim 14 , wherein a thickness of the first silicon nitride layer is 100nm to 800nm.

16. The TFT substrate according to claim 1 , wherein a thickness of the first silicon nitride layer is 100nm to 800nm.

17. The TFT substrate according to claim 1 , further comprising at least one of a under coating layers formed between the first and second barrier coating layers and the substrate.

18. The TFT substrate according to claim 17 , wherein the first and second hard coating layers comprise an acryl resin.

19. The TFT substrate according to claim 17 , wherein the first and second barrier coating layers comprise at least one of an inorganic nitride layer, an inorganic oxide layer, and an organic layer comprising acrylic layer.

20. The TFT substrate according to claim 19 , wherein the first and second barrier coating layers are a two-layer structure composed of the organic layer and an inorganic layer.

21. The TFT substrate according to claim 17 , wherein the first and second barrier coating layers comprise a third silicon nitride layer with a third refractive index larger than the second refractive index.

22. The TFT substrate according to claim 1 , wherein the first and second hard coating layers comprise an organic layer.

23. A TFT substrate comprising:

a plastic insulation substrate;

a first barrier coating layer formed on one surface of the plastic insulation substrate;

a first hard coating layer formed on the first barrier coating layer;

a stress relaxation layer with a positive intrinsic stress value, formed on the first hard coating layer;

a TFT comprising an inorganic layer with a negative intrinsic stress value, wherein the inorganic layer is formed on the stress relaxation layer;

a second barrier coating layer formed on the other surface of the plastic insulation substrate; and

a second hard coating layer formed on the second barrier coating layer.

24. The TFT substrate according to claim 23 , wherein the inorganic layer comprises at least one of an insulation layer, a semiconductor layer and an ohmic contact layer.

25. The TFT substrate according to claim 23 , wherein a refractive index of the stress relaxation layer is smaller than a refractive index of the inorganic layer.

26. The TFT substrate according to claim 25 , wherein the stress relaxation layer is made of silicon nitride and its refractive index is 1.9 or less.

27. A thin film transistor (TFT) substrate comprising:

a plastic insulation substrate having two surfaces;

a barrier coating layer and a hard coating layer formed on each of the surfaces;

a stress relaxation layer with a positive intrinsic stress value, formed on one of the hard coating layers; and

a TFT having a gate electrode and a gate insulation layer with a negative intrinsic stress value, wherein the gate insulation layer is formed on the stress relaxation layer,

wherein a nitrogen content of the stress relaxation layer is larger than a nitrogen of the gate insulation layer.

28. The TFT substrate according to 27 , wherein a refractive index of the gate insulation layer is larger than a refractive index of the stress relaxation layer.