CMOS image sensor and method of fabricating the same
View Patent ↗A CMOS image sensor and a method of fabricating the same are provided. In the CMOS image sensor, a device isolation layer is formed in a substrate to define an active region, and a photodiode is formed in the active region. A floating diffusion region is formed at a position spaced apart from the photodiode, and first and second gates are overlapped with one end of the photodiode and one end of the floating diffusion region, respectively. A third gate is disposed between the first gate and the second gate and overlapped with an upper portion of the device isolation layer and a predetermined portion of the floating diffusion region. An insulating layer is formed on the resulting structure where the third gate is formed. A buried contact has a first contact and a second contact, which are sequentially stacked to pass through the insulating layer and the third gate and to connect the third gate to the floating diffusion region disposed under the third gate.
1. A CMOS image sensor comprising:
a device isolation layer formed in a substrate to define an active region;
a photodiode formed in the active region;
a floating diffusion region formed at a position spaced apart from the photodiode;
a first gate formed between the photodiode and the floating diffusion region;
a second gate formed at a side of the floating diffusion region;
a third gate disposed between the first gate and the second gate and overlapped with an upper portion of the device isolation layer and a predetermined portion of the floating diffusion region;
an insulating layer formed on a resulting structure where the third gate is formed; and
a buried contact having a first contact and a second contact, the first contact and the second contact being sequentially stacked to pass through the insulating layer and the third gate and to connect the third gate to the floating diffusion region disposed under the third gate.
2. The CMOS image sensor according to claim 1 , wherein the first gate is a transfer gate, the second gate is a reset gate, and the third gate is a drive gate.
3. The CMOS imager sensor according to claim 2 , wherein each of the first gate, the second gate, and the third gate has a stacked structure of a gate dielectric layer and a gate electrode, the gate electrode having a multi-layer structure in which a polysilicon layer and a metal layer are sequentially stacked.
4. The CMOS image sensor according to claim 1 , wherein the first gate, the second gate, and the third gate have spacers on sidewalls thereof.
5. The CMOS image sensor according to claim 1 , wherein a diameter of the second contact is greater than or equal to that of the first contact.
6. The CMOS image sensor according to claim 1 , wherein the buried contact is formed by wholly or partially overlapping the first contact with the second contact.
7. The CMOS image sensor according to claim 6 , wherein when the first contact and the second contact are partially overlapped with each other, the first contact and the second contact are overlapped in a moving direction of electrons.
8. The CMOS image sensor according to claim 1 , wherein the substrate is formed using a semiconductor layer, the semiconductor layer being formed by stacking a highly doped P++ layer and a P-epi layer in sequence.