Predictive signal cancellation for extracting 1 Mb/s MIL-STD-1553 component from composite high performance 1553 signal

1. Apparatus for synthesizing a first analog signal for use in the analysis of a second analog signal combined with said first signal, said second signal being a higher frequency than said first signal, comprising:

a unit for receiving said combined signals;

first and second output lines coupled to an output of said receiving unit;

a high pass filter coupled to said first output line for passing said composite signals and filtering out harmonics of said second signal;

a low pass filter coupled to said second output line for filtering out the second signal;

a summing circuit having first and second inputs;

a delay circuit coupling an output of said high pass filter to said first input of said summing circuit;

a zero-crossing detector coupled to an output of said low pass filter for detecting zero crossings in a positive and negative going direction of a signal passed by said low pass filter;

a generator responsive to non-inverted and inverted outputs of the zero-crossing detector for generating a digital representation of a version of said first signal passing said low pass filter;

a unit for adjusting the digital representation to compensate for a timing skew between said signals in said first and second lines so that the signals in said first and second lines are in time synchronism when they reach said summing circuit;

a D/A converter for converting the digital representation of said first signal to an analog signal; and

said summing circuit canceling the analog signal generated by the D/A converter from the output of said high pass filter.

2. The apparatus of claim 1 further comprising a unit for analyzing an output of said summing circuit.

3. The apparatus of claim 1 further comprising a unit for storing the digital representation of said first signal outputted by said generator for use in subsequent cancellations.

4. The apparatus of claim 1 wherein said generator is configured to generate a digital output every N×500 nanoseconds, where N=1, 2, 3, or 4, responsive to each rising edge of a zero crossing detector output from a zero-crossing detector which monitors the output of the low pass filter.

5. The apparatus of claim 1 wherein the first signal provides data at a rate of 1 Mb/sec.

6. The apparatus of claim 5 further comprising a sampling clock having an operating frequency in the range of 80 to 100 MHz for synchronizing operation of said generator.

7. The apparatus of claim 1 further comprising:

an A/D converter for converting the output of said summing circuit into a digital format.

8. The apparatus of claim 7 further comprising a processor for extracting data from the output of said A/D converter.

9. The apparatus of claim 8 wherein said processor is a digital signal processor (DSP).

10. The apparatus of claim 1 , further comprising:

an updating circuit for updating the synthesized first signal;

a monitor for monitoring incoming signals to activate said updating circuit when only said first signal is present;

said updating circuit generating a model for the synthesized signal when activated by said monitor; and

an automatic gain control amplifier coupled between said summing circuit and said AID converter, being operative for normal operation when both of said first and second signals are received and being maintained at a minimum gain when only said first signal is present.

11. The apparatus of claim 10 , further comprising:

a sampling clock for providing sampling pulses to said generator and second converter for generating symbols at a rate controlled by said sampling clock.

12. The apparatus of claim 11 wherein said sampling clock generates sampling pulses at a rate greater than the frequency of said second signal.

13. The apparatus of claim 12 wherein the first signal has an operating frequency of 1 MHz, said second signal has an operating frequency in the range 8-20 MHz.

14. The apparatus of claim 13 wherein said sampling clock generates pulses at a rate in the range of 80-100 MHz.

15. The apparatus of claim 10 wherein said updating circuit comprises:

a unit for generating coefficients from a first signal received from a remote transmitter for modeling pulses obtained from positive and negative transitions of the received first signal to obtain an initial model of said first signal;

a unit responsive to obtaining said initial model of said first signal for initiating a closed-loop mode, to subtract the initial model of the first signal from the output of said delay circuit;

said updating circuit adjusting said coefficients responsive to a difference signal generated at the output of said second converter to null said difference signal; and

a storing unit for storing said coefficients.

16. The apparatus of claim 15 wherein said updating circuit further comprises:

a unit responsive to the simultaneous presence of said first and second signals for applying the synthesized signal to the generator to cancel the synthesized signal from the combined first and second signals passed by said delay circuit.

17. The apparatus of claim 10 wherein said updating circuit generates a synthesized signal which simulates a first signal passing said delay circuit with said second signal.

18. The apparatus of claim 11 wherein the updating circuit further comprises a timing skew measurement circuit; and

a phase-locked loop coupled to said sampling clock for generating a clock pulse;

said timing skew measurement circuit determining the time delay between rising edges of outputs of the zero-crossing detection circuit at a next rising edge of a pulse from said sampling clock.

19. A method for canceling out one of first and second data carrying signals transmitted as a combined signal to a receiver, said second signal having a frequency greater than said first signal, comprising:

transferring the combined signals received to first and second paths for further processing;

passing said first signal and filtering out said second signal from passing along said first path;

passing said combined first and second signals along said second path for further processing while filtering out harmonics of said second signal from passing along said second path;

transferring said first and second signals in said first path to a summing circuit after a given delay;

determining zero crossings of said first signal passed in said second path;

utilizing the zero crossings to generate a digital signal simulating the signal passed by said first path wherein rising edges of the zero crossings serve as starting points for digital representations of the positive and negative pulses, and responsive to: an identity of a terminal that is currently transmitted; a position of word/bits within a transmission of a current message from a terminal; values of prior Manchester half bits and sink types; and an identification of types of signal transitions;

adjusting time delays of the generated digital signal to eliminate any time skew between first signals in the first and second signal paths;

converting the generated digital signal into analog form;

subtracting the analog form of the digital signal from the combined first and second signals transferred from said first path; and

converting a resulting difference signal into digital form.

20. The method of claim 19 further comprising:

obtaining data contained in said digital difference signal.

21. The method of claim 19 further comprising:

adjusting a timing skew of the generated digital signal when the difference signal is greater than a given threshold.

22. The method of claim 19 further comprising:

adjusting the generated digital signal by repeating the method steps of claim 19 to further reduce the difference signal.

23. The method of claim 19 further comprising:

digitally processing the digital difference signal to provide a data bit stream of data in the first frequency signal.

24. The method of claim 19 further comprising:

disabling the step of utilizing the zero crossing to generate a digital signal responsive to absence of said first signal being transmitted to said receiver.

25. The method of claim 19 , further comprising:

measuring a time delay between a rising edge of a start of negative going zero crossing and a start of the generated digital signal and a time delay between a rising edge of a positive going zero crossing and a start of a positive pulse of the generated digital signal.

26. The method of claim 19 , further comprising:

storing the generated digital signal for subsequent use.

27. A method for generating a predictive cancellation signal, comprising:

receiving a composite signal comprised of a first and a second data carrying signal, a frequency of said second signal being greater than a frequency of said first signal;

separating said first signal from said first and second signals;

detecting positive and negative zero crossings of the separated first signal to synthesize an estimate of said first signal; and

subtracting the synthesized signal from said composite signal to recover said second signal.

28. Apparatus for synthesizing a first signal for use in the analysis of a composite signal comprised of a second signal combined with said first signal, said second signal having a higher frequency than said first signal, comprising:

a unit for receiving said combined signals in analog form;

an A/D converter for converting the combined signals;

first and second output lines coupled to an output of said AID converter;

a high pass filter coupled to said first output line for removing harmonics of the second signal;

a low pass filter coupled to said second output line for removing the second signal;

a summing circuit having first and second inputs;

a delay circuit coupling an output of said high pass filter to said first input of said summing circuit to synchronize arrival of the signals at said first and second inputs;

a zero-crossing detector coupled to an output of said low pass filter for detecting zero crossings in a positive and negative going direction of a signal passed by said low pass filter;

a generator for generating a digital output representation of said first signal responsive to said zero-crossing detector;

a circuit for adjusting the digital output of said generator to compensate for a timing skew between said signals in said first and second lines so that the signals in said first and second lines are in time synchronism when they reach said summing circuit; and

said summing circuit subtracting the output of said generator from said combined first and second signals.

29. The apparatus of claim 28 , further comprising:

a digital memory for storing the generated digital signal for subsequent use.

30. The apparatus of claim 28 , further comprising:

a digital signal processor (DSP) for retrieving data from said second signal.