IP Library Granted Patent US 7,423,317
Granted Patent B2
US 7,423,317 · App. 11/491,743 · Granted Sep 9, 2008

Split electrode gate trench power device

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Quick Facts
Patent No.
US 7,423,317
App. No.
11/491,743
Granted
Sep 9, 2008
Kind
B2
Abstract

A power semiconductor device which includes gate liners extending along gate insulation liners and an insulation block spacing the two gate liners.

Claims (19)

1. A power semiconductor device, comprising: a semiconductor body including a drift region of one conductivity, and a base region of another conductivity; a gate trench extending at least through said base region; gate insulation liner lining at least the sidewalls of said gate trench; a gate electrode adjacent each said gate insulation liner; an insulation block interposed between said gate electrodes and adjacent each gate electrode; a conductive regions of said one conductivity adjacent said gate trench; and a first power electrode electrically connected to said conductive regions; and a connector connecting said gate electrodes, wherein said connector is proud of said semiconductor body, is not wider than said gate trench, and includes a silicided top portion.

2. The device of claim 1 , wherein said device is a power MOSFET.

3. The device of claim 1 , further comprising an insulation body at the bottom of said gate trench, said insulation body being thicker than said gate insulation liners.

4. The device of claim 3 , wherein said gate insulation liners, said insulation block, and said insulation body are comprised of an oxide.

5. The device of claim 1 , further comprising a substrate of said one conductivity, said semiconductor body being disposed on said substrate and further comprising a second power electrode electrically connected to said substrate.

6. The device of claim 5 , wherein said first power electrode is a source electrode, said second power electrode is a drain electrode, and said conductive regions are source regions.

7. The device of claim 1 , wherein said sidewalls of said gate trench are tapered.

8. A method of fabricating a power semiconductor device, comprising:

forming a trench mask that includes and opening over a semiconductor body that includes a drift region and a base region adjacent said drift region;

forming a trench at bottom of said opening that extends through said base region;

oxidizing at least the sidewalls of said trench to form gate liners adjacent said sidewalls;

covering said oxidized sidewalls with an electrically conductive material to form gate electrodes;

depositing an insulation block between said gate liners electrodes and adjacent each gate liner electrode;

depositing conductive material inside said open to link said gate electrodes with a conductive connector, said conductive connector extending above said semiconductor body;

and removing said trench mask to obtain a conductive connector that is proud of said semiconductor body.

9. The method of claim 8 , further comprising forming an insulation body at the bottom of said trench, said insulation body being thicker than said gate liners.

10. The method of claim 8 , said conductive material comprises conductive polysilicon.

11. The method of claim 8 , wherein said gate liners are proud of said semiconductor body.

12. The method of claim 8 , further comprising siliciding a top portion of said connector.

Assignments (2)
CHANGE OF NAME Recorded Jul 23, 2018
From: INTERNATIONAL RECTIFIER CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 046612/0968 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2006
From: BURKE, HUGO R.G.; JONES, DAVID PAUL; MONTGOMERY, ROBERT; MA, LING
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 018285/0755 →