Computer system having a flash memory storage device
View Patent ↗A computer system is provided, wherein a storage device having a flash memory as the main medium is given a cache memory with a high hit rate even in a small capacity and less access overheads, high-speed writing to the flash memory is attained, and the number of rewriting is reduced: wherein a processing device, a cache memory and a flash memory for data via the cache memory to be written in response to a request from the processing device are provided; and a line size of an entry to the cache memory is 1/N (note that N is 2 or larger integer) of an actual page size as a writing unit of the flash memory.
1. A computer system, comprising:
a processing device;
a cache memory; and
a flash memory for data via the cache memory to be written in response to a request from the processing device;
wherein a line size of an entry to the cache memory is 1/N (where N is integer of 2 or larger) of an actual page size as a collective writing unit of the flash memory.
2. A computer system as set forth in claim 1 , further including a page a page buffer storing data of an actual page; wherein
when writing to the flash memory data of an entry to the cache memory, an entry part in the cache memory and a non-entry part in the flash memory in actual page data corresponding to the entry are combined in the page buffer and written to the flash memory after the combining.
3. A computer system as set forth in claim 2 , wherein the cache memory has a set associative structure, and the number of sets is N or an integral multiple of N.
4. A computer system as set forth in claim 2 , having a function part writing back at least two of entries at a time to the flash memory when there are a plurality of entries corresponding to different regions on the same actual page in the cache memory.
5. A computer system as set forth in claim 2 , wherein the flash memory is written back of actual page data performed by adding updated page data to a region subjected to erasing and invalidating an original page field.
6. A computer system, comprising:
a processing device;
a cache memory;
a flash memory for data via the cache memory to be written in response to a request from the processing device; and
a buffer;
wherein one entry of the cache memory includes a plurality of sectors and updating is performed in units of a sector; and
when writing to the flash memory data of an entry to the cache memory, an updated sector in the cache memory and non-updated sector in the flash memory are combined in the buffer and written to the flash memory after the combining.
7. A computer system as set forth in claim 6 , further including a page buffer storing data of an actual page; wherein
one entry of the cache memory includes a plurality of sectors and updating is performed in units of a sector; and
when writing to the flash memory data of an entry to the cache memory, an updated sector in the entry in the cache memory and non-updated sector in the flash memory are combined in the page buffer and written to the flash memory after the combining.
8. A computer system as set forth in claim 7 , wherein a line size of an entry to the cache memory is 1/N (where N is integer of 2 or larger) of an actual page size as a collective writing unit of the flash memory.
9. A computer system as set forth in claim 8 , wherein the cache memory has a set associative structure, and the number of sets is N or an integral multiple of N.
10. A computer system as set forth in claim 9 , having a function part writing back at least two of entries at a time to the flash memory when there are a plurality of entries corresponding to different regions on the same actual page in the cache memory.
11. A computer system, comprising:
a processing device;
a cache memory;
a flash memory for data via the cache memory to be written in response to a request from the processing device; and
a page buffer;
wherein the computer system has a function part temporarily storing in the page buffer continuous data in an amount of a multiple of a line size of an entry to the cache memory and simultaneously writing it to the flash memory.
12. A computer system as set forth in claim 11 , wherein
when writing to the flash memory data of an entry to the cache memory, an entry part in the cache memory and a non-entry part in the flash memory in actual page data corresponding to the entry are combined in the page buffer and written to the flash memory after the combining.
13. A computer system as set forth in claim 12 , wherein the cache memory has a set associative structure, and the number of sets is N or an integral multiple of N.
14. A computer system as set forth in claim 13 , having a function part writing back at least two of entries at a time to the flash memory when there are a plurality of entries corresponding to different regions on the same actual page in the cache memory.
15. A computer system as set forth in claim 11 , wherein a line size of an entry to the cache memory is 1/N (where N is integer of 2 or larger) of an actual page size as a collective writing unit of the flash memory.