Liquid crystal display device
View Patent ↗An LCD with reduced power consumption is described. The LCD includes a liquid crystal panel having a plurality of gate lines and data lines, a data driver supplying a data voltage to the plurality of data lines, a controller generating a current control signal to control an output terminal of the data driver so that the output terminal operates during a first period in which data is outputted from the data driver, and the output terminal does not operate during a second period in which data is not outputted from the data driver, and a gate driver that supplies a scan signal to the plurality of the gate lines.
1. A liquid crystal display device comprising:
a liquid crystal panel having a plurality of gate lines and data lines;
a data driver including a digital-to analog converter (DAC) supplying a data voltage to the plurality of data lines;
first switches between the data lines;
a second switch connecting one of the data lines;
third switches on the data lines between the DAC and the liquid crystal panel;
a buffer unit on the data lines between the DAC and the third switches;
a gate driver supplying a scan signal to the plurality of the gate lines; and
a controller that generates at least three signals for driving the liquid crystal panel during first to third periods,
wherein the buffer unit comprises:
a plurality of output buffers corresponding to the data lines; and
a current source between a controller and the output buffers,
wherein during the first period, the first switches are turned on under the control of a first signal to be short-circuited between the data lines and then charge the data lines with a common voltage, the second switch is turned off under the control of a second signal, the third switches are turned off under the control of a third signal, and the output buffers are inactivated under the control of a driving current from the current source under the control of a fourth signal.
2. The liquid crystal display device according to claim 1 , wherein during the second period, the first switches are turned on under the control of the first signal to be short-circuited between the data lines, the second switch is turned on under the control of the second signal to charge the data lines with a pre-charge voltage, the third switches are turned off under the control of the third signal, and the output buffers are inactivated under the control of the driving current from the current source under the control of the fourth signal.
3. The liquid crystal display device according to claim 2 , wherein during the third period, the first switches are turned off under the control of the first signal to be disconnected between the data lines, the second switch is turned off under the control of the second signal, the third switches are turned on under the control of the third signal, and the output buffers are activated under the control of the driving current from the current source under the control of the fourth signal to supply the data voltage from the DAC to the data lines.
4. A liquid crystal display device comprising:
a liquid crystal panel having a plurality of gate lines and data lines;
a data driver including a digital-to analog converter (DAC) supplying a data voltage to the plurality of data lines;
first switches between the data lines;
a second switch connecting one of the data lines;
third switches on the data lines between the DAC and the liquid crystal panel;
a buffer unit on the data lines between the DAC and the third switches;
a gate driver supplying a scan signal to the plurality of the gate lines; and
a controller that generates at least three signals for driving the liquid crystal panel during first to third periods,
wherein the buffer unit comprises:
a plurality of output buffers corresponding to the data lines;
a current source connected to the controller; and
a fourth switch between the current source and the output buffers,
wherein during the first period, the first switches are turned on under the control of a first signal to be short-circuited between the data lines and then charge the data lines with a common voltage, the second switch is turned off under the control of a second signal, the third switches are turned off under the control of a third signal, the fourth switch is turned off under the control of the third signal to be disconnected between the current source and the output buffers, and the output buffers are inactivated in the absence of a driving current from the current source.
5. The liquid crystal display device according to claim 4 , wherein during the second period, the first switches are turned on under the control of the first signal to be short-circuited between the data lines, the second switch is turned on under the control of the second signal to charge the data lines with a pre-charge voltage, the third switches are turned off under the control of the third signal, the fourth switch is turned off under the control of the third signal, and the output buffers and the output buffers are inactivated in the absence of the driving current from the current source.
6. The liquid crystal display device according to claim 5 , wherein during the third period, the first switches are turned off under the control of the first signal to be disconnected between the data lines, the second switch is turned off under the control of the second signal, the third switches are turned on under the control of the third signal, the fourth switch is turned on under the control of the third signal to supply the driving current to the output buffers, and the output buffers are activated under the control of the driving current to supply the data voltage from the DAC to the data lines.
7. A liquid crystal display device comprising:
a liquid crystal panel having a plurality of gate lines and data lines;
a data driver including a digital-to analog converter (DAC) supplying a data voltage to the plurality of data lines;
first switches between the data lines;
a second switch connecting one of the data lines;
third switches on the data lines between the DAC and the liquid crystal panel;
a buffer unit on the data lines between the DAC and the third switches;
a gate driver supplying a scan signal to the plurality of the gate lines; and
a controller that generates at least three signals for driving the liquid crystal panel during first to third periods,
wherein the buffer unit comprises:
a plurality of output buffers corresponding to the data lines;
a current source connected to the data lines; and
a fourth switch between the controller and the current source,
wherein during the first period, the first switches are turned on under the control of a first signal to be short-circuited between the data lines and then charge the data lines with a common voltage, the second switch is turned off under the control of a second signal, the third switches are turned off under the control of a third signal, the fourth switch is turned off under the control of the third signal to be disconnected between the controller and the current source, and the output buffers are inactivated in the absence of the fourth signal.
8. The liquid crystal display device according to claim 7 , wherein during the second period, the first switches are turned on under the control of the first signal to be short-circuited between the data lines, the second switch is turned on under the control of the second signal to charge the data lines with a pre-charge voltage, the third switches are turned off under the control of a third signal, the fourth switch is turned off under the control of the third signal to be disconnected between the controller and the current source, and the output buffers are inactivated in the absence of the fourth signal.
9. The liquid crystal display device according to claim 8 , wherein during the third period, the first switches are turned off under the control of the first signal to be disconnected between the data lines, the second switch is turned off under the control of the second signal, the third switches are turned on under the control of a third signal, the fourth switch is turned on under the control of the third signal to be short-circuited between the controller and the current source, and the output buffers are activated under the control of the driving current from the current source under the control of the fourth signal to supply the data voltage from the DAC to the data lines.