Memory

1. A memory comprising:

an access control portion performing an internal access operation on the basis of an external access operation;

a refresh control portion performing a refresh operation; and

a refresh division control portion dividing said refresh operation into a read operation and a rewrite operation,

for performing said read operation and said rewrite operation at least either before or after different said internal access operations corresponding to different said external access operations respectively.

2. The memory according to claim 1 , wherein

said refresh division control portion divides said rewrite operation into a first rewrite operation for writing a first data and a second rewrite operation for writing a second data, and

the memory performs said read operation, said first rewrite operation and said second rewrite operation at least either before or after different said internal access operations corresponding to different said external access operations respectively.

3. The memory according to claim 1 , further comprising a latch portion holding data read by said read operation of said refresh operation.

4. The memory according to claim 1 , further comprising:

an external access detection portion detecting said external access operation, and

a refresh determination portion determining whether or not to perform said refresh operation on the basis of detection of said external access operation by said external access detection portion and the operating state of said access control portion, wherein

said access control portion performs said refresh operation at least either before or after said internal access operation on the basis of the result of determination of said refresh determination portion.

5. The memory according to claim 4 , wherein

said refresh determination portion outputs a signal for said refresh operation if said access control portion performs neither said internal access operation nor said refresh operation when said external access detection portion detects said external access operation.

6. The memory according to claim 4 , wherein

said access control portion performs next said internal access operation after termination of previous said internal access operation or said refresh operation if performing said previous internal access operation or said refresh operation when said external access detection portion detects said external access operation.

7. The memory according to claim 1 , further comprising an external access counter portion counting the access frequency of said external access operation, wherein

said access control portion performs said refresh operation on the basis of said access frequency counted by said external access counter portion.

8. The memory according to claim 1 , performing said refresh operation regardless of the access frequency of said external access operation.

9. The memory according to claim 1 , further comprising:

a bit line and a word line arranged to intersect with each other, and

a memory cell arranged on the intersectional position between said bit line and said word line, wherein

said internal access operation includes:

a read operation,

a rewrite operation, and

an additional cycle for applying a voltage to said word line and said bit line for canceling potential difference applied to selected said memory cell in said read operation and said rewrite operation of said internal access operation when the memory performs no said refresh operation.

10. The memory according to claim 1 , wherein

said rewrite operation of said refresh operation includes a first rewrite operation for writing a first data and a second rewrite operation for writing a second data, and

the memory performs said read operation of said refresh operation at least either before or after a first internal access operation corresponding to a first external access operation, and

performs said first rewrite operation and said second rewrite operation of said refresh operation at least either before or after a second internal access operation corresponding to a second external access operation.

11. The memory according to claim 1 , further comprising a plurality of memory cell blocks each including a plurality of word lines,

for performing said refresh operation on said word lines included in each of at least two of said memory cell blocks when performing said refresh operation along with said internal access operation in the period of prescribed said external access operation.

12. The memory according to claim 11 , activating said word lines included in each of said at least two memory cell blocks subjected to said refresh operation at different rise timings when performing said refresh operation along with said internal access operation in said period of said prescribed external access operation.

13. The memory according to claim 12 , further comprising a delay circuit.

14. The memory according to claim 1 , wherein

said access control portion includes an internal clock generation portion.

15. The memory according to claim 1 , wherein

said refresh division control portion divides said rewrite operation into a first rewrite operation for writing first data and a second rewrite operation for writing second data, and

the memory performs divided said refresh operation every time said external access operation is performed a prescribed number of times.

16. The memory according to claim 1 , further comprising:

a bit line and a word line arranged to intersect with each other, and

a memory cell arranged on the intersectional position between said bit line and said word line, wherein

said refresh division control portion divides said rewrite operation into a first rewrite operation for writing a first data and a second rewrite operation for writing a second data, and

said access control portion adds an additional cycle to said internal access operation for applying a voltage to said word line and said bit line for canceling potential difference applied to selected said memory cell in said refresh operation.

17. The memory according to claim 1 , further comprising:

a word line and a bit line arranged to intersect with each other, and

a memory cell linked to at least said word line, and

performing said refresh operation on said memory cell linked to said word line.

18. The memory according to claim 1 , further comprising a switching portion switching between a first row address signal corresponding to an internal address signal for said internal access operation and a second row address signal corresponding to a refresh address signal for said refresh operation.

19. The memory according to claim 1 , wherein

said internal access operation includes a data read operation and a data rewrite operation as well as a data write operation.

20. The memory according to claim 1 , performing said read operation and said rewrite operation after different said internal access operations corresponding to different said external access operations respectively.