High-resolution broadband ADC
An analog-to-digital converter (ADC) uses a combination of sampling circuits and ADCs to convert the signal from analog to digital. By sampling an analog signal with a single front-end sampling circuit, the ADC substantially eliminates the dynamic error that is normally associated with mismatched parallel sampling circuits. The clean signal is then sampled a second time. Several sampling circuits arranged in parallel can be used to increase the bandwidth of the circuit. After the analog signal is sampled it is then converted to a time-interleaved digital signal. The ADC is able to achieve high-resolution broadband signal conversion while consuming much less power than other high-performance ADCs in systems such as GaAs and InP.
1 . An analog-to-digital converter (ADC) that provides a digital output signal in response to an analog input signal, comprising:
a front-end sampling circuit connected to accept said input signal and generate a static sampled signal; and
a plurality of ADCs arranged in parallel, each of said ADCs connected to receive said static sampled signal, said plurality of ADCs outputting interleaved digital signals.
2 . The ADC of claim 1 , wherein said front-end sampling circuit comprises a track-and-hold (T/H) sampler.
3 . The ADC of claim 1 , further comprising:
a serializer circuit connected to convert said interleaved digital signals to at least one serial digital signal.
4 . The ADC of claim 1 , wherein said plurality of ADCs comprises low-power silicon pipelined ADCs.
5 . The ADC of claim 1 , further comprising:
a timing circuit connected to provide a clock signal to the components of said ADC.
6 . The ADC of claim 5 , said timing circuit further comprising:
a low-jitter clock driver connected to provide said clock signal; and
a clock distribution circuit connected to distribute said clock signal to said components of said ADC.
7 . An analog-to-digital converter (ADC) that provides a digital output signal in response to an analog input signal, comprising:
a front-end sampling circuit, connected to accept said input signal and generate an intermediate sampled signal;
a plurality of decimating sampling circuits arranged in parallel, each of said decimating sampling circuits connected to receive said intermediate sampled signal and generate a final sampled signal; and
a plurality of ADCs arranged in parallel, each of said ADCs receiving said final sampled signal and outputting an interleaved digital signal.
8 . The ADC of claim 7 , wherein said front-end sampling circuit comprises a track-and-hold (T/H) sampler circuit.
9 . The ADC of claim 7 , wherein said decimating sampling circuits comprise track-and-hold (T/H) sampler circuits.
10 . The ADC of claim 7 , further comprising:
a timing circuit connected to provide a clock signal to said ADC.
11 . The ADC of claim 7 , further comprising:
a serializer circuit, converting said interleaved digital signal to at least one serial digital signal.
12 . The ADC of claim 7 , wherein said decimating sampling circuits sample said intermediate sampled signal in an ordered sequence with a substantially uniform delay between samples.
13 . A control system, comprising:
an analog input signal;
a timing circuit connected to provide a clock signal to said control system;
a first-tier sampling circuit connected to accept said analog input signal;
a plurality of second-tier sampling circuits driven by said first-tier sampling circuit;
a plurality of analog-to-digital converters (ADCs) driven by said second-tier sampling circuits, said plurality of ADCs connected to output interleaved digital signals;
a processor connected to accept signals from said plurality of ADCs; and
a load circuit controlled by said processor.
14 . The control system of claim 13 , further comprising:
a serializer circuit connected to accept a plurality of interleaved digital signals from said second-tier sampling circuits, and outputting to said processor at least one serial digital signal.
15 . The control system of claim 13 , wherein said first-tier sampling circuit comprises a wide-band track-and-hold (T/H) circuit.
16 . The control system of claim 13 , wherein said second-tier sampling circuits are T/H circuits.
17 . The control system of claim 13 , wherein said ADCs are high-resolution, low-speed ADCs.
18 . The control system of claim 13 , said timing circuit further comprising:
a low-jitter clock driver; and
a clock distribution network.
19 . The control system of claim 13 , wherein said plurality of second-tier sampling circuits samples a signal from said first-tier sampling circuit in an ordered sequence with a substantially uniform delay between samples.
20 . A method for converting an analog signal to a digital signal, comprising:
inputting an analog signal;
sampling said analog signal to produce a static sampled signal;
quantizing said sampled signal to produce a quantized interleaved signal; and
outputting at least one digital signal.
21 . The method of claim 20 , wherein said analog signal is sampled with wide-band sampling circuit.
22 . The method of claim 20 , wherein said static sampled signal is input to a set of sampling circuits, each of said sampling circuits outputting a sampled portion of the static sampled signal.
23 . The method of claim 22 , wherein said sampling circuits are track-and-hold (T/H) circuits.
24 . The method of claim 20 , wherein said quantized interleaved signal is serialized such that said at least one digital signal is a serial digital signal.
25 . The method of claim 20 , wherein said ADCs are low-power silicon pipelined ADCS.
26 . An analog-to-digital converter, comprising:
at least one first-tier sampling circuit;
at least one second-tier sampling circuit connected with said at least one first-tier sampling circuit to output a sampled signal;
wherein said first- and second-tier sampling circuits are connected such that the dynamic error is substantially eliminated from said sampled signal.