Data driver capable of an offset compensation and display apparatus having the same

1. A data driver comprising:

a digital-analog converter that receives image data to convert the image data into an analog voltage; and

a buffer that outputs a second power source voltage based on a first power source voltage and a first amplified voltage corresponding to the analog voltage, and outputs a first power source voltage based on a second power source voltage and a second amplified voltage corresponding to the analog voltage.

2. The data driver of claim 1 , wherein the buffer comprises:

a biasing section that outputs first and second bias currents based on the first and second power source voltages;

a first differential amplifying section that outputs the first amplified voltage based on the first bias current when the analog voltage is applied to the first differential amplifying section;

a second differential amplifying section that outputs the second amplified voltage based on the second bias current when the analog voltage is applied to the second differential amplifying section; and

an output section that outputs the second power source voltage based on the first amplified voltage and the first power source voltage, and outputs the first power source voltage based on the second amplified voltage and the second power source voltage.

3. The data driver of claim 2 , wherein the output section comprises:

a first output compensating section that outputs the first power source voltage and feeds back the first power source voltage to the first and second differential amplifying sections based on the second amplified voltage and the second power source voltage; and

a second output compensating section that outputs the second power source voltage and feeds back the second power source voltage to the first and second differential amplifying sections based on the first amplified voltage and the first power source voltage.

4. The data driver of claim 3 , wherein the first output compensating section comprises:

a first P-MOS transistor including a first current electrode that is electrically connected to the first power source voltage, and a control electrode that is electrically connected to the second differential amplifying section; and

a second P-MOS transistor including a first current electrode that is electrically connected to a second current electrode of the first P-MOS transistor, a control electrode that is electrically connected to the second power source voltage, and a second current electrode that is electrically connected to an output terminal of the output section, and first and second differential amplifying sections.

5. The data driver of claim 4 , wherein the second output compensating section comprises:

a first N-MOS transistor including a first current electrode that is electrically connected to the second power source voltage, and a control electrode that is electrically connected to the first differential amplifying section; and

a second N-MOS transistor including a first current electrode that is electrically connected to a second current electrode of the first N-MOS transistor, a control electrode that is electrically connected to the first power source voltage, and a second current electrode that is electrically connected to an output terminal of the output section, and first and second differential amplifying sections.

6. The data driver of claim 2 , wherein the biasing section comprises:

a first current mirror that provides the first bias current to the first differential amplifying section based on the first power source voltage;

a second current mirror that provides the second bias current to the second differential amplifying section based on the second power source voltage; and

a bias compensating section that is electrically connected to the first and second current mirrors to control outputs of the first and second bias currents.

7. The data driver of claim 6 , wherein the bias compensating section comprises:

a P-MOS transistor including a control electrode that is electrically connected to the second power source voltage, and a first current electrode that is electrically connected to an output terminal of the first current mirror to receive a second current from the first current mirror; and

a N-MOS transistor including a control electrode that is electrically connected to the first power source voltage, and a first current electrode that is electrically connected to a second current electrode of the P-MOS transistor.

8. A display apparatus comprising:

a display panel including a data line, a scan line and a switching device formed in a region defined by the data line and the scan line;

a timing control section that outputs image data, and first and second timing signals;

a scan driver that outputs scan signal that activates the scan line based on the first timing signal; and

a data driver including a digital-analog converter that receives the image data to convert the image data into an analog voltage and a buffer that outputs a second power source voltage based on a first power source voltage and a first amplified voltage corresponding to the analog voltage and outputs a first power source voltage based on a second power source voltage and a second amplified voltage corresponding to the analog voltage.

9. The display apparatus of claim 8 , wherein the display panel is a liquid crystal display panel having a liquid crystal capacitor that is electrically connected to the switching device.

10. The display apparatus of claim 8 , wherein the data driver is formed on the display panel.

11. The display apparatus of claim 8 , wherein the data driver comprises polysilicon thin film transistor.