Method and apparatus for data encryption
View Patent ↗A method and apparatus for use in encrypting and decrypting digital communications converting an initial block to final block based on freely selectable control information and secret key information having double the length of prior art keys and maintaining compatibility with the prior art encryption system.
1. A method of transmitting cryptographically secured digital communications comprising:
(a) encrypting a digital signal with a first block cipher hardware device that is computationally a function of a first fixed length selectively variable key;
(b) effectively inhibiting the operation of the most downstream of modulo operators in a second block cipher hardware device that is computationally a function of a second fixed length selectively variable key different from the first fixed length selectively variable key; and,
(c) decrypting the encrypted digital signal with the second block cipher hardware device.
2. The method of claim 1 wherein the step of effectively inhibiting further comprises modifying the key of the second block cipher hardware device to conform to two sequential iterations of the key of the first block cipher hardware device.
3. The method of claim 1 wherein a length of the first and second fixed length selectively variable keys is selectable.
4. A plural block cipher hardware device, cryptographically secured digital communication system comprising:
(a) a first block cipher hardware device that is computationally a function of a first fixed length selectively variable key to encrypt and decrypt a digital signal; and,
(b) a second block cipher hardware device that is computationally a function of a second fixed length selectively variable key different from the first fixed length selectively variable key to encrypt and decrypt a digital signal;
wherein the second block cipher hardware device is compatible with the first block cipher hardware device as the second fixed length selectively variable key comprises two sequential iterations of the first fixed length selectively variable key such that an operation of the most downstream of modulo operators of the second block cipher hardware device is effectively inhibited.
5. The system of claim 4 wherein a length of the first and second fixed length selectively variable keys is selectable.
6. The system of claim 5 wherein the length of either of the first or second fixed length selectively variable keys is 256 bits.
7. The system of claim 5 wherein the length of either of the first or second fixed length selectively variable keys is 128 bits.
8. The system of claim 5 wherein the length of either of the first or second fixed length selectively variable keys is 64 bits.
9. A plural block cipher hardware device, cryptographically secured digital communication system comprising:
a first block cipher hardware device that is computationally a function of a first fixed length selectively variable key to encrypt and decrypt a digital signal; and,
a second block cipher hardware device that is computationally a function of a second fixed length selectively variable key different from the first fixed length selectively variable key to encrypt and decrypt a digital signal;
wherein a length of the first and second fixed length selectively variable keys is selectable, and wherein the second block cipher hardware device is compatible with the first block cipher hardware device as the second fixed length selectively variable key comprises two sequential iterations of the first fixed length selectively variable key such that an operation of the most downstream of modulo operators of the second block cipher hardware device is effectively inhibited.
10. The system of claim 9 wherein the length of either of the first or second fixed length selectively variable keys is 256 bits.
11. The system of claim 9 wherein the length of either of the first or second fixed length selectively variable keys is 128 bits.
12. The system of claim 9 wherein the length of either of the first or second fixed length selectively variable keys is 64 bits.