Random access memory controller with out of order execution
View Patent ↗A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge in an order that can be different from the order of the corresponding client transactions. The command scheduler may also re-order memory access commands such as read and write. The slicing and out-of-order command scheduling allow a reduction in memory latency. The data transfer to and from clients can be kept in order.
1. A data processing system comprising:
a data processing client;
a random access memory for performing a memory operation in response to a client request made by the client, the memory including a plurality of banks, each of the banks including a plurality of pages; and
a memory controller connected to the client and the memory, for controlling the memory to perform the memory operation according to the client request, wherein the memory controller comprises
slicing logic for slicing a complex memory access request derived from the client request into a plurality of simple memory access requests each corresponding to a set of memory addresses within a single page within one of the banks, the complex memory access request corresponding to more than one page, the plurality of simple memory access requests including a plurality of preparatory parts and a corresponding plurality of memory access parts, each simple memory access request including a preparatory part and a memory access part; and
command ordering logic connected to the slicing logic, for controlling an ordering of the plurality of preparatory parts in a first order different from a second order of the plurality of memory access parts.
2. The system of claim 1 , wherein each preparatory part comprises a command selected from an activate command and a precharge command.
3. The system of claim 2 , wherein each memory access part comprises a command selected from a read command and a write command.
4. The system of claim 1 , wherein controlling the ordering of the plurality of preparatory parts in the first order different from the second order of the plurality of memory access parts comprises:
assigning a priority to at least part of each of the simple requests; and
arbitrating a transmission of the at least part of each of the simple requests to the memory according to the priority.
5. The system of claim 1 , wherein:
the system comprises a plurality of data processing clients connected to the memory controller; and
the memory controller further comprises client arbitration logic connected to the clients, for arbitrating a plurality of memory access requests received from the clients.
6. The system of claim 5 , wherein the memory controller further comprises virtual-to-physical address translation logic connected to the client arbitration logic and slicing logic, for receiving a plurality of virtual memory access commands from the client arbitration logic, translating the virtual memory access commands into a corresponding plurality of physical memory access commands, and transmitting the plurality of physical memory access commands to the slicing logic.
7. The system of claim 1 , wherein the random access memory comprises a dynamic random access memory.
8. The system of claim 7 , wherein the dynamic random access memory comprises a synchronous dynamic random access memory.
9. The system of claim 8 , wherein the synchronous dynamic random access memory comprises a double data rate synchronous random access memory.
10. The system of claim 1 , wherein the second order of the plurality of memory access parts is different from an order of the plurality of simple memory access requests within the complex memory access request.
11. A random access memory controller for controlling a random access memory comprising a plurality of banks according to commands received from a plurality of clients, comprising:
slicing logic for slicing a complex memory access request derived from a client request into a plurality of simple memory access requests each corresponding to a set of memory addresses within a single page within one of the plurality of banks, the complex memory access request corresponding to more than one page within the random access memory, the plurality of simple memory access requests including a plurality of preparatory parts and a corresponding plurality of memory access parts, each simple memory access request including a preparatory part and a memory access part; and
command ordering logic connected to the slicing logic, for controlling an ordering of the plurality of preparatory parts in a first order different from a second order of the plurality of memory access parts.
12. The controller of claim 11 , wherein each preparatory part is selected from an activate and a precharge command.
13. The controller of claim 12 , wherein each memory access part is selected from a read and a write command.
14. The controller of claim 11 , wherein controlling the ordering of the plurality of preparatory parts in the first order different from the second order of the plurality of memory access parts comprises:
assigning a priority to at least part of each of the simple requests; and
arbitrating a transmission of the at least part of each of the simple requests to the memory according to the priority.
15. The controller of claim 11 , wherein the second order of the plurality of memory access parts is different from an order of the plurality of simple memory access requests within the complex memory access request.
16. A dynamic random access memory controller for controlling a dynamic random access memory comprising a plurality of banks, each bank including a plurality of pages, the memory controller comprising:
a client arbiter for ordering a plurality of client memory access requests, each request including a virtual memory address;
a virtual to physical address translation unit connected to the client arbiter, for translating the virtual memory address to a physical memory address, thereby generating a complex memory transaction;
a transaction slicer connected to the virtual to physical address translation unit, for slicing the complex memory transaction into a plurality of simple transaction slices, each simple transaction slice corresponding to a set of memory addresses within a single page within one of the banks, the complex transaction corresponding to more than one page within the dynamic random access memory;
a command scheduler connected to the transaction slicer, for generating a plurality of physical memory commands derived from the transaction slices, wherein the command scheduler is capable of ordering a set of preparatory memory commands in an order different from an order of a set of corresponding memory access commands of the transaction slices; and
a command arbiter connected to the command scheduler and to the dynamic random access memory, for allowing only one memory command received from the command scheduler to be transmitted to the dynamic random access memory at any time.
17. A random access memory control method comprising:
slicing a complex memory access request into a plurality of simple memory access requests each corresponding to a set of memory addresses within a single page within one bank of a multi-bank random access memory, the complex memory access request corresponding to more than one page within the random access memory, the plurality of simple memory access requests including a plurality of preparatory parts and a corresponding plurality of memory access parts, each simple memory access request including a preparatory part and a memory access part; and
controlling an ordering of the plurality of preparatory parts in a first order different from a second order of the plurality of memory access parts.
18. The method of claim 17 , wherein each preparatory part comprises a command selected from an activate command and a precharge command.
19. The method of claim 18 , wherein each memory access part comprises a command selected from a read command and a write command.
20. The method of claim 17 , wherein controlling the ordering of the plurality of preparatory parts in the first order different from the second order of the plurality of memory access parts comprises:
assigning a priority to at least part of each of the simple requests; and
arbitrating a transmission of the at least part of each of the simple requests to the memory according to the priority.
21. The method of claim 17 , wherein the second order of the plurality of memory access parts is different from an order of the plurality of simple memory access requests within the complex memory access request.
22. A data processing system comprising:
a plurality of clients for generating a plurality of client requests; and
a random access memory controller connected to the plurality of clients and comprising command reordering logic configured to receive a plurality of memory access requests derived from the plurality of client requests, each memory access request including a preparatory part and a memory access part, the command reordering logic being configured to control an ordering of a set of preparatory parts in a first order, and a set of memory access parts corresponding to the set of preparatory parts in a second order different from the first order.