IP Library Granted Patent US 7,825,885
Granted Patent B2
US 7,825,885 · App. 11/499,509 · Granted Nov 2, 2010

Display device

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Quick Facts
Patent No.
US 7,825,885
App. No.
11/499,509
Granted
Nov 2, 2010
Kind
B2
Abstract

A display device having a pixel section pixel circuits, scan lines, capacity lines, a drive circuit driving the scan lines and the capacity lines selectively, a generation circuit generating a common voltage signal switching in level at a predetermined cycle, and a correction circuit correcting the signals driving the capacity lines of the drive circuit, wherein each pixel circuit contains a display element and holding capacitor, a first pixel electrode of the display element pixel cell, a first electrode of the holding capacitor, and one terminal of the switching element are connected, a second electrode of the holding capacitor is connected to the capacity lines arrayed in a corresponding row, and the common voltage signal is applied in a second pixel electrode of the display element. The correction circuit has a monitor circuit monitoring the pixel potential of the pixel section and correcting a signal driving the capacity lines taking into consideration the optical characteristics of the display element based on the monitor result of the monitor circuit.

Claims (19)

1. A display device comprising:

a pixel section having a plurality of pixel circuits, each writing video pixel data propagated through a switching element over a signal line, arranged in a matrix,

a plurality of scan lines arranged so as to correspond to an array of rows of the pixel circuits and control conduction of the switching elements,

a plurality of capacity lines arranged so as to correspond to an array of rows of the pixel circuits,

a drive circuit for selectively driving the plurality of scan lines and the plurality of capacity lines,

a generation circuit for generating a common voltage signal switched in level at a predetermined cycle, and

a correction circuit for correcting the signals driving the capacity lines of the drive circuit, wherein

each pixel circuit arrayed at the pixel section includes

a display element having a first pixel electrode and second pixel electrode and

a holding capacitor having a first electrode and second electrode,

a first pixel electrode of the display element pixel cell and a first electrode of the holding capacitor are connected to one terminal of the switching element,

a second electrode of the holding capacitor is connected to the capacity line arrayed at a corresponding row,

a second pixel electrode of the display element is supplied with the common voltage signal,

the drive circuit has a capacity line driver which drives a corresponding capacity line independently for each row based on a polarity signal at the time of a pixel write operation wherein values for corrected signals driving the capacity lines are determined at least in part based upon a predetermined temperature relationship; and further wherein the common voltage signal is a small amplitude signal;

the drive circuit has a capacity line driver which determines a polarity of a signal driving a capacity line based on the polarity at the time of a pixel write operation;

the drive circuit has a scan line driver including a shift register for shifting a predetermined signal in a column direction and a buffer receiving the signal of the shift register and driving the corresponding scan line, and

the capacity line driver includes a first latch latching the polarity signal based on an output signal of the shift register to the buffer and a second latch latching and outputting the polarity signal latched by the first latch based on a shift signal to a next stage of the shift register.

2. A display device as set forth in claim 1 , wherein the drive circuit drives the scan lines of the selected row, writes pixel data into the desired pixel circuits, then drives the capacity lines of the same row.

3. A display device as set forth in claim 1 , wherein the drive circuit selects as a signal for driving a capacity line one of a first level and a second level lower than the first level and applies it to the corresponding capacity line.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2013
From: SONY CORPORATION
To: JAPAN DISPLAY WEST INC.
Reel/Frame 031377/0874 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2006
From: SATO, TOMOHIKO; ITAKURA, NAYOUKI; TAKEUCHI, TAKEYA; FUKANO, TOMOYUKI
To: SONY CORPORATION
Reel/Frame 018345/0843 →