Method and apparatus for controlling phase of a clock signal
A method and corresponding apparatus are disclosed for controlling the phase of a second clock signal from (i) a first clock signal of different frequency and (ii) a synchronization signal. One example embodiment recovers a first clock signal from a bus carrying data and detects a synchronization signal. Both the first clock signal and the synchronization signal are provided to a clock generator, which then generates the second clock signal with a phased based on the first clock signal and the synchronization signal. The use of the example embodiment is a low cost way to easily control the phase of a second clock signal with minimal added components and/or additional signal processing.
1 . A method of controlling phase of a clock signal, comprising:
basing a frequency of a second clock signal in a second direction on a frequency of a first clock signal in a first direction; and
controlling a phase of the second clock signal based on a synchronization signal used for synchronizing communications in the second direction.
2 . The method according to claim 1 , wherein controlling the phase of the second clock signal includes detecting a start-of-frame indicator from a signal carrying data in the first direction.
3 . The method according to claim 2 , wherein detecting the start-of-frame comprises detecting a start-of-frame for each frame indicator included in the data.
4 . The method according to claim 1 , wherein the phase of the second clock signal is based on a signal representing an event not embedded in a data in the first direction.
5 . The method according to claim 1 , wherein the first clock signal is a downstream clock signal and the second clock signal is an upstream clock signal.
6 . The method according to claim 1 , further including generating the second clock signal comprising:
recovering the first clock signal from a bus carrying data;
detecting the synchronization signal;
providing the first clock signal and the synchronization signal to a clock generator; and
generating the second clock signal with a phased based on the first clock signal and the synchronization signal.
7 . The method according to claim 6 , wherein the first clock signal has a first clock frequency and generating the second clock signal includes dividing the frequency of the first clock signal by an integer N.
8 . The method according to claim 7 , wherein the clock generator is a modulo N counter.
9 . The method according to claim 8 , wherein the first clock frequency is higher than the second clock frequency.
10 . An apparatus for controlling a phase of a clock signal, comprising:
a clock recoverer including an input coupled to a bus carrying data and an output providing a first clock signal recovered from the data;
a signal detector including an output providing a synchronization signal detected for use in synchronizing communications; and
a clock generator having an input coupled to the output of the clock recoverer to receive the first clock signal, a reset input coupled to the synchronization signal, and an output providing the second clock signal based on the first clock signal and having a phase controlled as a function of the synchronization signal.
11 . The apparatus according to claim 10 , wherein the synchronization signal represents an event not embedded in the data.
12 . The apparatus according to claim 10 , wherein the synchronization signal is a start-of-frame indicator from the data.
13 . The apparatus according to claim 10 , wherein the clock generator is a frequency divider circuit.
14 . The apparatus according to claim 10 , wherein the clock generator is a modulo N counter.
15 . The apparatus according to claim 10 , configured to operate in an optical network terminal.
16 . The optical network terminal according to claim 15 , wherein the second clock signal is used for transmitting a bus carrying data from the optical network terminal to an optical line terminal.
17 . The optical network terminal according to claim 16 , wherein transmission of busses carrying data between the optical line terminal and an optical network terminal is transmitted through an optical distribution network.
18 . The optical network terminal according to claim 17 , wherein the optical distribution network includes at least one optical splitter.
19 . The optical network terminal according to claim 16 , further including a transceiver configured to transmit the bus carrying data from an optical network terminal to the optical line terminal in Ethernet frame units.
20 . The optical network according to claim 16 , further including a transceiver configured to transmit the bus carrying data from an optical network terminal to the optical line terminal in ATM cells.
21 . The optical network terminal according to claim 16 , further including a transceiver configured to transmit the bus carrying data from an optical network terminal to the optical line terminal using a TDMA protocol.
22 . A method of controlling a phase of a clock signal, comprising:
determining a variable bit delay of a second clock signal relative to a first clock signal, the first clock signal being frequency locked; and
delaying the second clock signal by the variable bit delay to control a phase of the second clock signal.
23 . The method according to claim 22 , wherein the variable bit delay is determined by sampling the second clock signal at a frequency of the first clock signal.
24 . The method according to claim 22 , wherein the variable bit delay is determined by measuring a difference between a frequency of the second clock signal and the frequency of the first clock signal and calculating the variable bit delay.
25 . The method according to claim 22 , wherein a second clock signal frequency is a non-integer multiple of a first clock signal frequency.
26 . An apparatus for controlling a phase of a clock signal, comprising:
a clock recoverer including an input coupled to a bus carrying data and an output providing a first clock signal recovered from the data;
a variable bit delay generator to determine a variable bit delay of a second clock signal relative to a first clock signal, the first clock signal being frequency locked; and
a variable shift register to delay the second clock signal by the variable bit delay to control a phase of the second clock signal.
27 . The apparatus according to claim 26 , wherein the variable bit delay generator samples the second clock signal at a first clock signal frequency to determine the variable bit delay.
28 . The apparatus according to claim 26 , wherein the variable bit delay generator measures a difference between a second clock signal frequency and a first clock signal frequency to determine the variable bit delay.
29 . The apparatus according to claim 26 , configured to operate in an optical network terminal.