Dual printhead controller architecture
View Patent ↗Dual printhead controller architecture includes a master central processor capable of being interfaced with a first printhead. A slave central processor is capable of being interfaced with a second printhead. Data transfer means is operatively connected between the master central processor and the slave central processor to permit communication between the master and slave central processors. A host link is operatively connected to the master central processor to permit the master central processor to receive page data from a host processor.
1. Dual printhead controller architecture that comprises
a master central processor capable of being interfaced with a first printhead;
a slave central processor capable of being interfaced with a second printhead;
data transfer means operatively connected between the master central processor and the slave central processor to permit communication between the master and slave central processors; and
a host link operatively connected to the master central processor to permit the master central processor to receive page data from a host processor.
2. Dual printhead controller architecture as claimed in claim 1 , in which the master and slave central processors are configured to be interfaced with respective printheads that incorporate pagewidth arrays of micro-electromechanical ink jet printing mechanisms.
3. Dual printhead controller architecture as claimed in claim 1 , in which the data transfer means is in the form of a serial link interposed between the master and slave central processors.
4. Dual printhead controller architecture as claimed in claim 1 , in which a master memory is connected to the master central processor, the master central processor being configured to store page data for both the printheads in the master memory.
5. Dual printhead controller architecture as claimed in claim 4 , in which a slave memory is connected to the slave central processor to receive page data for the printhead of the slave central processor from the master central processor.